Datasheet

W5500 Datasheet Version1.0.9 9 / 66
This pin must be connected to a 10nF capacitor.
This is the output voltage of the internal regulator.
23
RSVD
Pull-down
I
It must be tied to GND.
24
SPDLED
-
O
Speed LED
This shows the Speed status of the connected link.
Low: 100Mbps
High: 10Mbps
25
LINKLED
-
O
Link LED
This shows the Link status.
Low: Link is established
High: Link is not established
26
DUPLED
-
O
Duplex LED
This shows the Duplex status for the connected link.
Low: Full-duplex mode
High: Half-duplex mode
27
ACTLED
-
O
Active LED
This shows that there is Carrier sense (CRS) from the
active Physical Medium Sub-layer (PMD) during TX or RX
activity.
Low: Carrier sense from the active PMD
High: No carrier sense
28
VDD
-
PWR
Digital 3.3V Power
29
GND
-
GND
Digital Ground
30
XI/CLKIN
-
AI
Crystal input / External Clock input
External 25MHz Crystal Input.
This pin can also be connected to single-ended TTL
oscillator (CLKIN). 3.3V clock should be applied for the
External Clock input. If this method is implemented, XO
should be left unconnected.
Refer to the ‘Crystal reference schematic’ (Figure.3) for
details.
31
XO
-
AO
Crystal output
External 25MHz Crystal Output
Note: Float this pin if using an external clock being
driven through XI/CLKIN
32
SCSn
Pull-up
I
Chip Select for SPI bus
This pin can be asserted low to select W5500 in SPI
interface.
Low: selected