Datasheet

W5500 Datasheet Version1.0.9 61 / 66
5.5.4 SPI Timing
Figure 23. SPI Timing
5
Theoretical Guaranteed Speed
Even though theoretical design speed is 80MHz, the signal in the high speed may be distorted because
of the circuit crosstalk and the length of the signal line. The minimum guaranteed speed of the SCLK
is 33.3 MHz which was tested and measured with the stable waveform.
Please refer to the SPI Application Note which shows the WIZnet test environment and results.
6
2.1ns is when pn loaded with 30pF. The time is shorter with lower capacitance.
SCSn
SCLK
MOSI
MISO
T
WH
T
WL
HI-Z
HI-Z
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
T
DS
T
DH
T
OH
T
CHZ
T
OV
T
CSS
T
CS
T
CSH
Symbol
Description
Min
Max
Units
F
SCK
SCK Clock Frequency
80/33.3
5
MHz
T
WH
SCK High Time
6
ns
T
WL
SCK Low Time
6
ns
T
CS
SCSn High Time
30
ns
T
CSS
SCSn Setup Time
5
-
ns
T
CSH
SCSn Hold Time
5
ns
T
DS
Data In Setup Time
3
ns
T
DH
Data In Hold Time
3
ns
T
OV
Output Valid Time
5
ns
T
OH
Output Hold Time
0
ns
T
CHZ
SCSn High to Output Hi-Z
2.1
6
ns