Datasheet
Table Of Contents
34 / 66 W5500 Datasheet Version1.0.9
INTLEVEL (Interrupt Low Level Timer Register) [R/W] [0x0013 – 0x0014] [0x0000]
INTLEVEL configures the Interrupt Assert Wait Time (I
AWT
). When the next interrupt
occurs, Interrupt PIN (INTn ) will assert to low after INTLEVEL time.
3
(when INTLEVEL > 0)
Equation 1 Interrupt Assert Wait Time
Figure 21. INTLEVEL Timing
a. When Timeout Interrupt of Socket 0 is occurred, S0_IR[3] & SIR[0] bit set as ‘1’ and
then INTn PIN is asserted to low.
b. When the connection interrupt of Socket 1 is occurred before the previous interrupt
processing is not completed, S1_IR[0] & SIR[1] bits set as ‘1’ and INTn PIN is still low.
c. If the host processed the previous interrupt completely by clearing the S0_IR[3] bit,
INTn PIN is de-asserted to high but S1_IR[0] & SIR[1] is still set as ‘1’.
d. Although S1_IR[0] & SIR[1] bit is set as ‘1’, the INTn can’t be asserted to low during
INTLEVEL time. After the INTLEVEL time expires, the INTn will be asserted to low.
3
is 150MHz
PLL_CLK
SIR
S0_IR
S1_IR
0x0000
0x0001 0x0002
0x04
0x00
0x01
0x00
0x00
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
0x0003
INTn
a.
b.
c. d.
I
AWT