Datasheet

30 / 66 W5500 Datasheet Version1.0.9
3.2 Socket Register Block
W5500 supports 8 Sockets for communication channel. Each Socket is controlled by
Socket n Register Block(when 0≤n≤7). The n value of Socket n Register can be selected
by BSB[4:0] of SPI Frame. Table 4 defines the 16bits Offset Address of registers in
Socket n Register Block.
Refer to ‘Chapter 4.2’ for more details about each register.
Table 4. Offset Address in Socket n Register Block (0≤n≤7)
Offset
Register
Offset
Register
Offset
Register
0x0000
Socket n Mode
(Sn_MR)
0x0010
0x0011
Socket n Destination Port
(Sn_DPORT0)
(Sn_DPORT1)
0x0024
0x0025
Socket n TX Write
Pointer
(Sn_TX_WR0)
(Sn_TX_WR1)
0x0001
Socket n Command (Sn_CR)
0x0012
0x0013
Socket n
Maximum Segment Size
(Sn_MSSR0)
(Sn_MSSR1)
0x0026
0x0027
Socket n RX Received
Size
(Sn_RX_RSR0)
(Sn_RX_RSR1)
0x0002
Socket n Interrupt
(Sn_IR)
0x0003
Socket n Status
(Sn_SR)
0x0028
0x0029
Socket n RX Read Pointer
(Sn_RX_RD0)
(Sn_RX_RD1)
0x0014
Reserved
0x0004
0x0005
Socket n Source Port
(Sn_PORT0)
(Sn_PORT1)
0x0015
Socket n IP TOS
(Sn_TOS)
0x002A
0x002B
Socket n RX Write
Pointer
(Sn_RX_WR0)
(Sn_RX_WR1)
0x0016
Socket n IP TTL
(Sn_TTL)
0x0006
0x0007
0x0008
0x0009
0x000A
0x000B
Socket n Destination
Hardware Address
(Sn_DHAR0)
(Sn_DHAR1)
(Sn_DHAR2)
(Sn_DHAR3)
(Sn_DHAR4)
(Sn_DHAR5)
0x0017
~
0x001D
Reserved
0x002C
Socket n Interrupt Mask
(Sn_IMR)
0x002D
0x002E
Socket n Fragment
Offset in IP header
(Sn_FRAG0)
(Sn_FRAG1)
0x001E
Socket n Receive Buffer
Size
(Sn_RXBUF_SIZE)
0x001F
Socket n
Transmit Buffer Size
(Sn_TXBUF_SIZE)
0x002F
Keep alive timer
(Sn_KPALVTR)
0x000C
0x000D
0x000E
0x000F
Socket n
Destination IP Address
(Sn_DIPR0)
(Sn_DIPR1)
(Sn_DIPR2)
(Sn_DIPR3)
0x0020
0x0021
Socket n TX Free Size
(Sn_TX_FSR0)
(Sn_TX_FSR1)
0x0030
~
0xFFFF
Reserved
0x0022
0x0023
Socket n TX Read Pointer
(Sn_TX_RD0)
(Sn_TX_RD1)