Datasheet

16 / 66 W5500 Datasheet Version1.0.9
11000
Reserved
11001
Selects Socket 6 Register
11010
Selects Socket 6 TX Buffer
11011
Selects Socket 6 RX Buffer
11100
Reserved
11101
Selects Socket 7 Register
11110
Selects Socket 7 TX Buffer
11111
Selects Socket 7 RX Buffer
If the Reserved Bits are selected, it can cause the mal-function of the
W5500.
2
RWB
Read/Write Access Mode Bit
This sets Read/Write Access Mode.
‘0’ : Read
‘1’ : Write
1~0
OM [1:0]
SPI Operation Mode Bits
This sets the SPI Operation Mode.
SPI Operation Mode supports two modes, the Variable Length Data Mode
and the Fixed Length Data Mode.
- Variable Length Data Mode (VDM)
: Data Length is controlled by SCSn.
External Host makes SCSn Signal Assert (High-to-Low) and informs
the start of the SPI Frame Address Phase to W5500.
Then the external host transfers the Control Phase with
OM[1:0]=’00’.
After N-Bytes Data Phase transfers, SCSn Signal is De-asserted (Low-
to-High) and informs the end of the SPI Frame Data Phase to W5500.
In VDM Mode, the SCSn must be controlled with SPI Frame unit by
the External Host. (Refer to the Figure 4)
- Fixed Length Data Mode (FDM)
: In FDM, the Data Length is set by OM[1:0], these are not ‘00’ value.
So, the SCSn signal should be Low state, and has one Length type
(among 1 Bytes, 2 Bytes, 4 Bytes) according to the OM[1:0] value.
(Refer to the Figure 5.)
The next table shows the SPI Operation Mode according to the OM[1:0].