Datasheet

W5500 Datasheet Version1.0.9 15 / 66
2.2.2 Control Phase
The Control Phase specifies the Block to which the Offset Address (set by Address
Phase) belongs, the Read/Write Access Mode and the SPI Operation Mode.
7
6
5
4
3
2
1
0
BSB4
BSB3
BSB2
BSB1
BSB0
RWB
OM1
OM0
Bit
Symbol
Description
7~3
BSB [4:0]
Block Select Bits
W5500 has Common Register, 8 Socket Register, TX/RX Buffer Block for
each Socket.
The next table shows the Block selected by BSB[4:0].
BSB [4:0]
Meaning
00000
Selects Common Register.
00001
Selects Socket 0 Register
00010
Selects Socket 0 TX Buffer
00011
Selects Socket 0 RX Buffer
00100
Reserved
00101
Selects Socket 1 Register
00110
Selects Socket 1 TX Buffer
00111
Selects Socket 1 RX Buffer
01000
Reserved
01001
Selects Socket 2 Register
01010
Selects Socket 2 TX Buffer
01011
Selects Socket 2 RX Buffer
01100
Reserved
01101
Selects Socket 3 Register
01110
Selects Socket 3 TX Buffer
01111
Selects Socket 3 RX Buffer
10000
Reserved
10001
Selects Socket 4 Register
10010
Selects Socket 4 TX Buffer
10011
Selects Socket 4 RX Buffer
10100
Reserved
10101
Selects Socket 5 Register
10110
Selects Socket 5 TX Buffer
10111
Selects Socket 5 RX Buffer