W5500 Datasheet Version 1.0.9 http://www.wiznet.co.kr © Copyright 2013 WIZnet Co., Ltd. All rights reserved.
W5500 The W5500 chip is a Hardwired TCP/IP embedded Ethernet controller that provides easier Internet connection to embedded systems. W5500 enables users to have the Internet connectivity in their applications just by using the single chip in which TCP/IP stack, 10/100 Ethernet MAC and PHY embedded. WIZnet‘s Hardwired TCP/IP is the market-proven technology that supports TCP, UDP, IPv4, ICMP, ARP, IGMP, and PPPoE protocols. W5500 embeds the 32Kbyte internal memory buffer for the Ethernet packet processing.
Target Applications W5500 is suitable for the following embedded applications: - Home Network Devices: Set-Top Boxes, PVRs, Digital Media Adapters - Serial-to-Ethernet: Access Controls, LED displays, Wireless AP relays, etc.
Block Diagram 4 / 66 W5500 Datasheet Version1.0.
Table of Contents Pin Assignment .......................................................................................... 7 1.1 Pin Descriptions .............................................................................. 7 HOST Interface ......................................................................................... 12 2.1 SPI Operation Mode ........................................................................ 13 2.2 SPI Frame ..........................................................
Table of Figures Figure 1. W5500 Pin Layout ....................................................................... 7 Figure 2. External reference resistor ......................................................... 11 Figure 3. Crystal reference schematic ........................................................ 11 Figure 4. Variable Length Data Mode (SCSn controlled by the host) .................... 12 Figure 5. Fixed Length Data Mode (SCSn is always connected by Ground) ............. 12 Figure 6.
AGND NC NC PMODE0 PMODE1 PMODE2 RSVD RSVD RSVD RSVD RSVD RSTn 48 47 46 45 44 43 42 41 40 39 38 37 Pin Assignment TXN 1 36 INTn TXP 2 35 MOSI AGND 3 34 MISO AVDD 4 33 SCLK RXN 5 32 SCSn RXP 6 31 XO DNC 7 30 XI/CLKIN AVDD 8 29 GND AGND 9 28 VDD EXRES1 10 27 ACTLED AVDD 11 26 DUPLED NC 12 25 LINKLED W5500 19 20 21 22 23 24 TOCAP AVDD 1V2O RSVD SPDLED 18 VBG AGND 17 AVDD 15 AVDD 16 14 AGND AGND 13 NC 48LQFP Figure 1.
Table 2. W5500 Pin Description Internal Pin No Symbol 1 TXN - AO TXP/TXN Signal Pair 2 TXP - AO The differential data is transmitted to the media on the Bias1 Type Description TXP/TXN signal pair. 3 AGND - GND Analog ground 4 AVDD - PWR Analog 3.3V power 5 RXN - AI RXP/RXN Signal Pair 6 RXP - AI The differential data from the media is received on the RXP/RXN signal pair. 7 DNC - AI/O Do Not Connect Pin 8 AVDD - PWR Analog 3.
This pin must be connected to a 10nF capacitor. This is the output voltage of the internal regulator. 23 RSVD Pull-down I It must be tied to GND. 24 SPDLED - O Speed LED This shows the Speed status of the connected link. Low: 100Mbps High: 10Mbps 25 LINKLED - O Link LED This shows the Link status. Low: Link is established High: Link is not established 26 DUPLED - O Duplex LED This shows the Duplex status for the connected link.
High: deselected 33 SCLK - I SPI clock input This pin is used to receive SPI Clock from SPI master. 34 MISO - O SPI master input slave(W5500) output When SCSn is Low, this pin outputs SPI data. When SCSn is High, this pin becomes High Impedance (logically disconnected).
The 12.4KΩ(1%) Resistor should be connected between EXRES1 pin and analog ground (AGND) as below. Figure 2. External reference resistor The crystal reference schematic is shown as below. Figure 3. Crystal reference schematic W5500 Datasheet Version1.0.
HOST Interface W5500 provides SPI (Serial Peripheral Interface) Bus Interface with 4 signals (SCSn, SCLK, MOSI, MISO) for external HOST interface, and operates as a SPI Slave. The W5500 SPI can be connected to MCU as shown in Figure 4 and Figure 5 according to its operation mode (Variable Length Data / Fixed Length Data Mode) which will be explained in Chapter 2.3 and Chapter 2.4. In Figure 4, SPI Bus can be shared with other SPI Devices.
The W5500 supports SPI Mode 0 and Mode 3. Both MOSI and MISO signals use transfer sequence from Most Significant Bit (MSB) to Least Significant Bit (LSB) when MOSI signal transmits and MISO signal receives. MOSI & MISO signals always transmit or receive in sequence from the Most Significant Bit (MSB) to Least Significant Bit (LSB). Sampling Toggling Toggling SCLK SCLK MISO/MOSI MISO/MOSI Mode 0 : SCLK idle level low Sampling Mode 3 : SCLK idle level high Figure 6. SPI Mode 0 & 3 2.
2.2 SPI Frame W5500 SPI Frame consists of 16bits Offset Address in Address Phase, 8bits Control Phase and N bytes Data Phase as shown in Figure 7. The 8bits Control Phase is reconfigured with Block Select bits (BSB[4:0]), Read/Write Access Mode bit (RWB) and SPI Operation Mode (OM[1:0]). Block Select bits select the block to which the Offset Address belongs.
2.2.2 Control Phase The Control Phase specifies the Block to which the Offset Address (set by Address Phase) belongs, the Read/Write Access Mode and the SPI Operation Mode. 7 6 5 4 3 2 1 0 BSB4 BSB3 BSB2 BSB1 BSB0 RWB OM1 OM0 Bit Symbol Description Block Select Bits W5500 has Common Register, 8 Socket Register, TX/RX Buffer Block for each Socket. The next table shows the Block selected by BSB[4:0]. BSB [4:0] 7~3 BSB [4:0] W5500 Datasheet Version1.0.
11000 Reserved 11001 Selects Socket 6 Register 11010 Selects Socket 6 TX Buffer 11011 Selects Socket 6 RX Buffer 11100 Reserved 11101 Selects Socket 7 Register 11110 Selects Socket 7 TX Buffer 11111 Selects Socket 7 RX Buffer If the Reserved Bits are selected, it can cause the mal-function of the W5500. Read/Write Access Mode Bit This sets Read/Write Access Mode. 2 RWB ‘0’ : Read ‘1’ : Write SPI Operation Mode Bits This sets the SPI Operation Mode.
2.2.3 OM[1:0] Meaning 00 Variable Data Length Mode, N-Bytes Data Phase (1 ≤ N) 01 Fixed Data Length Mode , 1 Byte Data Length (N = 1) 10 Fixed Data Length Mode , 2 Byte Data Length (N = 2) 11 Fixed Data Length Mode , 4 Byte Data Length (N = 4) Data Phase With the Control Phase set by the SPI Operation Mode Bits OM[1:0], the Data Phase is set by two types of length, one type is the N-Bytes length (VDM mode) and the other type is 1/2/4 Bytes (FDM mode).
2.3.1 Write Access in VDM SPI Frame Start SCSn shoud be remained low until SPI Frame Transmit done. SCSn MODE3 SCLK 0 1 2 12 13 14 15 16 17 18 19 20 21 22 24 25 23 27 28 26 29 30 31 2 1 0 MODE0 16 bits Offset Address MOSI 15 14 3 13 RWB OM[1:0] BSB[4:0] 2 1 0 4 3 2 0 1 8-bit Data 1 W 0 0 7 6 5 4 3 MISO SPI Frame End SCSn Should be remained low until SPI Frame Transmit done. SCSn 32 33 34 35 36 37 37 39 1 0 ...
1 Byte WRITE Access Example When the Host writes Data 0xAA to ‘Socket Interrupt Mask Register (SIMR) of Common Register Block by using VDM mode, the data is written with the SPI Frame below. Offset Address = 0x0018 BSB[4:0] = ‘00000’ RWB = ‘1’ OM[1:0] = ‘00’ 1st = 0xAA Data The External Host asserts (High-to-Low) SCSn before transmitting SPI Frame, then the Host transmits 1 bit with synchronizing the Toggle SCLK. The External Host deasserts (Low-to-High) the SCSn at the end of SPI Frame transmit.
N-Bytes WRITE Access Example When the Host writes 5 Bytes Data (0x11, 0x22, 0x33, 0x44, 0x55) to Socket 1’s TX Buffer Block 0x0040 Address by using VDM mode, 5 bytes data are written with the SPI Frame below. Offset Address = 0x0040 BSB[4:0] = ‘00110’ RWB = OM[1:0] = ‘00’ 1st Data = 0x11 2nd Data = 0x22 3rd Data = 0x33 4th Data = 0x44 5th = 0x55 Data ‘1’ The N-Bytes Write Access is shown in Figure 10.
2.3.2 Read Access in VDM SPI Frame Start SCSn shoud be remained low until SPI Frame Transmit & Receive done. SCSn MODE3 SCLK 0 1 2 12 13 14 16 15 17 18 19 20 21 22 27 28 24 25 26 23 29 30 31 2 1 0 MODE0 MOSI 15 14 3 13 RWB OM[1:0] BSB[4:0] 16bits Offset Address 2 1 0 4 3 2 0 R 0 1 8-bit Data 1 0 MISO 7 6 5 4 3 SPI Frame End SCSn Should be remained low until SPI Frame Transmit & Receive done. SCSn 32 33 34 35 36 37 38 ...
1 Byte READ Access Example When the Host reads the ‘Socket Status Register(S7_SR) of the Socket 7’s Register Block by using VDM mode, the data is read with the SPI Frame below. Let’s S7_SR to ‘SOCK_ESTABLISHED (0x17)’. Offset Address = 0x0003 BSB[4:0] = ‘11101’ RWB = ‘0’ OM[1:0] = ‘00’ 1st = 0x17 Data The External Host asserts (High-to-Low) SCSn signal before transmitting SPI Frame, then the Host transmits Address and Control Phase to W5500 through the MOSI signal.
N-Bytes Read Access Example When the Host reads 5 Bytes Data (0xAA, 0xBB, 0xCC, 0xDD, 0xEE) from the Socket 3’s RX Buffer Block 0x0100 Address by using VDM mode, 5 bytes data are read with the SPI Frame as below. Offset Address = 0x0100 BSB[4:0] = ‘01111’ RWB = ‘0’ OM[1:0] = ‘00’ 1st Data = 0xAA 2nd Data = 0xBB 3rd Data = 0xCC 4th Data = 0xDD 5th Data = 0xEE The N-Bytes Read Access is shown in Figure 13.
2.4 Fixed Length Data Mode (FDM) The FDM mode can be used when the External Host cannot control SCSn signal. The SCSn signal should be tied to Low (Always connected to GND) and it is not possible to share the SPI Bus with other SPI Devices. (Refer to the Figure 5) In VDM mode, Data Phase length is controlled by SCSn control. But in FDM mode, Data Phase length is controlled by OM[1:0] value (‘01’ / ‘10’ / ‘11’) which is the SPI Operation Mode Bits of the Control Phase.
2.4.1 Write Access in FDM 1 Bytes WRITE Access Figure 14. 1 Byte Data Write SPI Frame in FDM mode 2 Bytes WRITE Access Figure 15. 2 Bytes Data Write SPI Frame in FDM mode 4 Bytes WRITE Access Figure 16. 4 Bytes Data Write SPI Frame in FDM mode W5500 Datasheet Version1.0.
2.4.2 Read Access in FDM 1 Byte READ Access Figure 17. 1 Byte Data Read SPI Frame in FDM mode 2 Bytes READ Access Figure 18. 2 Bytes Data Read SPI Frame in FDM mode 4 Bytes READ Access Figure 19. 4 Bytes Data Read SPI Frame in FDM mode 26 / 66 W5500 Datasheet Version1.0.
Register and Memory Organization W5500 has one Common Register Block, eight Socket Register Blocks, and TX/RX Buffer Blocks allocated to each Socket. Each block is selected by the BSB[4:0](Block Select Bit) of SPI Frame. Figure 20 shows the selected block by the BSB[4:0] and the available offset address range of Socket TX/RX Buffer Blocks. Each Socket’s TX Buffer Block exists in one 16KB TX memory physically and is initially allocated with 2KB.
Block Select Bits 16bit Offset Address Valid Range Blocks 11111 (0x1F) Socket 7 RX Buffer 11110 (0x1E) Socket 7 TX Buffer 11101 (0x1E) Socket 7 Register 0xFFFF 0x3FFF 0x3E2C 0xF800 0xF7FF 0x3800 0xF000 0xEFFF 0x3000 ... ... 11100 (0x1C) Reserved Physical 16KB RX Memory 11011 (0x1B) Socket 6 RX Buffer Socket 7 RX Buffer 11010 (0x1A) Socket 6 TX Buffer 0x2000 ...
3.1 Common Register Block Common Register Block configures the general information of W5500 such as IP and MAC address. This block can be selected by the BSB[4:0] value of SPI Frame. Table 3 defines the offset address of registers in this block. Refer to ‘Chapter 4.1’ for more details about each register. Table 3.
3.2 Socket Register Block W5500 supports 8 Sockets for communication channel. Each Socket is controlled by Socket n Register Block(when 0≤n≤7). The n value of Socket n Register can be selected by BSB[4:0] of SPI Frame. Table 4 defines the 16bits Offset Address of registers in Socket n Register Block. Refer to ‘Chapter 4.2’ for more details about each register. Table 4.
3.3 Memory W5500 has one 16KB TX memory for Socket n TX Buffer Blocks and one 16KB RX memory for Socket n RX buffer Blocks. 16KB TX memory is initially allocated in 2KB size for each Socket TX Buffer Block (2KB X 8 = 16KB). The initial allocated 2KB size of Socket n TX Buffer can be re-allocated by using ‘Socket n TX Buffer Size Register (Sn_TXBUF_SIZE)’.
Register Descriptions 4.1 Common Registers MR (Mode Register) [R/W] [0x0000] [0x00] 2 MR is used for S/W reset, ping block mode and PPPoE mode. 7 6 5 4 3 2 1 0 RST Reserved WOL PB PPPoE Reserved FARP Reserved Bit Symbol 7 RST 6 Reserved Description If this bit is ‘1’, All internal registers will be initialized. It will be automatically cleared as ‘0’ after S/W reset.
0 : Disable Force ARP mode 1 : Enable Force ARP mode In Force ARP mode, It forces on sending ARP Request whenever data is sent. 0 Reserved Reserved GAR (Gateway IP Address Register) [R/W] [0x0001 – 0x0004] [0x00] GAR configures the default gateway address. Ex) In case of “192.168.0.1” 0x0001 0x0002 0x0003 0x0004 192 (0xC0) 168 (0xA8) 0 (0x00) 1 (0x01) SUBR (Subnet Mask Register) [R/W] [0x0005 – 0x0008] [0x00] SUBR configures the subnet mask address. Ex) In case of “255.255.255.
INTLEVEL (Interrupt Low Level Timer Register) [R/W] [0x0013 – 0x0014] [0x0000] INTLEVEL configures the Interrupt Assert Wait Time (IAWT). When the next interrupt occurs, Interrupt PIN (INTn ) will assert to low after INTLEVEL time. 𝐼𝐴𝑊𝑇 = (𝐼𝑁𝑇𝐿𝐸𝑉𝐸𝐿 + 1) × 1 𝑃𝐿𝐿𝑐𝑙𝑘 3 × 4 (when INTLEVEL > 0) Equation 1 Interrupt Assert Wait Time 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PLL_CLK SIR 0x0000 0x0001 S0_IR 0x00 0x04 S1_IR 0x00 0x0003 0x0002 0x00 b. 0x01 a. c. IAWT d. INTn Figure 21.
IR (Interrupt Register) [R/W] [0x0015] [0x00] IR indicates the interrupt status. Each bit of IR can be cleared when the host writes ‘1’ value to each bit. If IR is not equal to ‘0x00’, INTn PIN is asserted low until it is ‘0x00’. 7 6 CONFLICT Bit UNREACH 5 PPPoE 4 MP Symbol 3 Reserved 2 Reserved 1 Reserved 0 Reserved Description IP Conflict 7 CONFLICT Bit is set as ‘1’ when own source IP address is same with the sender IP address in the received ARP request.
IMR (Interrupt Mask Register) [R/W][0x0016][0x00] IMR is used to mask interrupts. Each bit of IMR corresponds to each bit of IR. When a bit of IMR is ‘1’ and the corresponding bit of IR is ‘1’, an interrupt will be issued. In other words, if a bit of IMR is ‘0’, an interrupt will not be issued even if the corresponding bit of IR is ‘1’.
SIR (Socket Interrupt Register) [R/W] [0x0017] [0x00] SIR indicates the interrupt status of Socket. Each bit of SIR be still ‘1’ until Sn_IR is cleared by the host. If Sn_IR is not equal to ‘0x00’, the n-th bit of SIR is ‘1’ and INTn PIN is asserted until SIR is ‘0x00’. 7 6 5 4 3 2 1 0 S7_INT S6_INT S5_INT S4_INT S3_INT S2_INT S1_INT S0_INT Bit Symbol 7 Description When the interrupt of Socket n occurs, the n-th bit of SIR becomes ~ Sn_INT ‘1’.
RTR (Retry Time-value Register) [R/W] [0x0019 – 0x001A] [0x07D0] RTR configures the retransmission timeout period. The unit of timeout period is 100us and the default of RTR is ‘0x07D0’ or ‘2000’. And so the default timeout period is 200ms(100us X 2000). During the time configured by RTR, W5500 waits for the peer response to the packet that is transmitted by Sn_CR(CONNECT, DISCON, CLOSE, SEND, SEND_MAC, SEND_KEEP command).
the TCP packet is retransmitted. The retransmission is repeated as many as ‘RCR+1’. Even after TCP retransmission is repeated as ‘RCR+1’ and there is no response to the TCP retransmission, the final timeout is occurred and Sn_IR(TIMEOUT) becomes ‘1’. The time of final timeout (TCPTO) of TCP retransmission is as below. 𝑀 𝑇𝐶𝑃𝑇𝑂 = (∑(𝑅𝑇𝑅 × 2𝑁 ) + ((𝑅𝐶𝑅 − 𝑀) × 𝑅𝑇𝑅𝑀𝐴𝑋 )) × 0.
PHAR (Destination Hardware Address Register in PPPoE mode) [R/W] [0x001E-0x0023] [0x0000] PHAR should be written to the PPPoE server hardware address acquired in PPPoE connection process Ex) In case that destination hardware address is 00:08:DC:12:34:56 0x001E 0x001F 0x0020 0x0021 0x0022 0x0023 0x00 0x08 0xDC 0x12 0x34 0x56 PSID (Session ID Register in PPPoE mode) [R/W] [0x0024-0x0025] [0x0000] PSID should be written to the PPPoE sever session ID acquired in PPPoE connection process.
UIPR (Unreachable IP Address Register) [R] [0x0028-0x002B] [0x00000000] UPORTR (Unreachable Port Register) [R] [0x002C-0x002D] [0x0000] W5500 receives an ICMP packet(Destination port unreachable) when data is sent to a port number which socket is not open and UNREACH bit of IR becomes ‘1’ and UIPR & UPORTR indicates the destination IP address & port number respectively. Ex) In case of “192.168.0.
PHYCFGR (W5500 PHY Configuration Register) [R/W] [0x002E] [0b10111XXX] PHYCFGR configures PHY operation mode and resets PHY. In addition, PHYCFGR indicates the status of PHY such as duplex, Speed, Link. Bit Symbol Description Reset [R/W] 7 RST When this bit is ‘0’, internal PHY is reset. After PHY reset, it should be set as ‘1’.
VERSIONR (W5500 Chip Version Register) [R] [0x0039] [0x04] VERSIONR always indicates the W5500 version as 0x04. W5500 Datasheet Version1.0.
4.2 Socket Registers Sn4_MR (Socket n Mode Register) [R/W] [0x0000] [0x00] Sn_MR configures the option or protocol type of Socket n. 7 MULTI/ MFEN Bit 6 BCASTB 5 4 ND / MC UCASTB /MMB MIP6B 3 2 1 0 P3 P2 P1 P0 Symbol Description Multicasting in UDP mode 0 : disable Multicasting 1 : enable Multicasting This bit is applied only during UDP mode(P[3:0] = ‘0010’).
When this bit is ‘1’, It sends the ACK packet without delay as soon as a Data packet is received from a peer. When this bit is ‘0’, It sends the ACK packet after waiting for the timeout time configured by RTR. Multicast 0 : using IGMP version 2 1 : using IGMP version 1 This bit is applied only during UDP mode(P[3:0] = ‘0010’) and MULTI = ‘1’. It configures the version for IGMP messages (Join/Leave/Report).
Sn_CR (Socket n Command Register) [R/W] [0x0001] [0x00] This is used to set the command for Socket n such as OPEN, CLOSE, CONNECT, LISTEN, SEND, and RECEIVE. After W5500 accepts the command, the Sn_CR register is automatically cleared to 0x00. Even though Sn_CR is cleared to 0x00, the command is still being processed. To check whether the command is completed or not, please check the Sn_IR or Sn_SR.
In these cases, Sn_SR is changed to SOCK_CLOSED. Valid only in TCP mode. Regardless of ‘TCP server’ or ‘TCP client’, the DISCON command processes the disconnect-process (‘Active close’ or ‘Passive close’). Active close: it transmits disconnect-request(FIN packet) to the connected peer Passive close: When FIN packet is received from peer, a FIN packet is replied back to the peer.
RECV completes the processing of the received data in Socket n RX Buffer by using a RX read pointer register (Sn_RX_RD). 0x40 RECV For more details, refer to Socket n RX Received Size Register (Sn_RX_RSR), Socket n RX Write Pointer Register (Sn_RX_WR), and Socket n RX Read Pointer Register (Sn_RX_RD). Sn_IR (Socket n Interrupt Register) [RCW1] [0x0002] [0x00] Sn_IR indicates the status of Socket Interrupt such as establishment, termination, receiving data, timeout).
Sn_SR (Socket n Status Register) [R] [0x0003] [0x00] Sn_SR indicates the status of Socket n. The status of Socket n is changed by Sn_CR or some special control packet as SYN, FIN packet in TCP. Value Symbol 0x00 SOCK_CLOSED Description This indicates that Socket n is released. When DISCON, CLOSE command is ordered, or when a timeout occurs, it is changed to SOCK_CLOSED regardless of previous status. 0x13 SOCK_INIT This indicates Socket n is opened with TCP mode.
0x42 SOCK_MACRAW This indicates Socket 0 is opened in MACRAW mode (S0_MR(P[3:0]) = ‘0100’)and is valid only in Socket 0. It changes to SOCK_MACRAW when S0_MR(P[3:0] = ‘0100’ and OPEN command is ordered. Like UDP mode socket, MACRAW mode Socket 0 can transfer a MAC packet (Ethernet frame) without the connectionprocess. The following table shows a temporary status indicated during changing the status of Socket n.
Sn_PORT (Socket n Source Port Register) [R/W] [0x0004-0x0005] [0x0000] Sn_PORT configures the source port number of Socket n. It is valid when Socket n is used in TCP/UDP mode. It should be set before OPEN command is ordered.
In TCP server mode, it indicates the port number of ‘TCP client’ after successfully establishing connection. In UDP mode, it configures the port number of peer to be transmitted the UDP packet by SEND/SEND_MAC command.
Socket n RX Buffer Block can be accessible with the 16bits Offset Address ranged from 0x0000 to 0xFFFF regardless of the configured size. (Refer to Sn_RX_RD & Sn_RX_WR). Value (dec) 0 1 2 4 8 16 Buffer size 0KB 1KB 2KB 4KB 8KB 16KB Ex) Socket 0 RX Buffer Size = 8KB 0x001E 0x08 Sn_TXBUF_SIZE (Socket n TX Buffer Size Register) [R/W] [0x001F] [0x02] Sn_TXBUF_SIZE configures the TX buffer block size of Socket n. Socket n TX Buffer Block size can be configured with 1,2,4,8, and 16 Kbytes.
SEND/SEND_MAC command after saving the data in Socket n TX buffer. But, if data is bigger than its checked size, transmit the data after dividing into the checked size and saving in the Socket n TX buffer. If Sn_MR(P[3:0]) is not TCP mode(‘0001’), it is automatically calculated as the difference between ‘Socket n TX Write Pointer (Sn_TX_WR)’ and ‘Socket n TX Read Pointer (Sn_TX_RD)’.
3. After saving the transmitting data, update Sn_TX_WR to the increased value as many as transmitting data size. If the increment value exceeds the maximum value 0xFFFF(greater than 0x10000 and the carry bit occurs), then the carry bit is ignored and will automatically update with the lower 16bits value. 4.
Sn_RX_WR is initialized by OPEN command and it is auto-increased by the data reception. If the increased value exceeds the maximum value 0xFFFF, (greater than 0x10000 and the carry bit occurs), then the carry bit is ignored and will automatically update with the lower 16bits value. Ex) In case of 2048(0x0800) in S0_RX_WR, 0x002A 0x002B 0x08 0x00 Sn_IMR (Socket n Interrupt Mask Register) [R/W] [0x002C] [0xFF] Sn_IMR masks the interrupt of Socket n. Each bit corresponds to each bit of Sn_IR.
Sn_KPALVTR (Socket n Keep Alive Time Register) [R/W] [0x002F] [0x00] Sn_KPALVTR configures the transmitting timer of ‘KEEP ALIVE(KA)’ packet of SOCKETn. It is valid only in TCP mode, and ignored in other modes. The time unit is 5s. KA packet is transmittable after Sn_SR is changed to SOCK_ESTABLISHED and after the data is transmitted or received to/from a peer at least once.
Electrical Specifications 5.1 Absolute Maximum Ratings Symbol Parameter Rating Unit VDD DC Supply voltage -0.5 to 4.6 V VIN DC input voltage -0.5 to 6 V DC output voltage -0.5 to 4.6 V IIN DC input current 5 mA TOP Operating temperature -40 to +85 C TJMAX Maximum junction temperature 125 C TSTG Storage temperature -65 to +150 C VOUT *COMMENT: Stressing the device beyond the ‘Absolute Maximum Ratings’ may cause permanent damage. 5.
5.3 DC Characteristics (Test Condition: Ta = –40 to 85°C) Symbol Parameter VDD Supply voltage VIH High level input Test Condition Apply VDD, AVDD Min Typ Max Unit 2.97 3.3 3.63 V 2.0 5.5 V - 0.3 0.8 V voltage VIL Low level input voltage VT Threshold point All inputs except XI 1.30 1.41 1.53 V VT+ Schmitt trig Low to All inputs except XI 1.53 1.64 1.73 V All inputs except XI 0.95 1.02 1.
5.4 Power Dissipation (Test Condition: VDD=3.3V, AVDD=3.3V, Ta = 25°C) Condition Min Typ Max Unit 100M Link - 128 - mA 10M Link - 75 - mA Un-Link (Auto-negotiation mode) - 65 - mA 100M Transmitting - 132 - mA 10M Transmitting - 79 - mA Power Down mode - 13 - mA 5.5 AC Characteristics 5.5.1 Reset Timing TRC RSTn TPL PLOCK (Internal) Figure 22. Reset Timing Symbol 5.5.
5.5.4 SPI Timing TCS SCSn VIH VIL TCSS SCLK TCSH VIH TWH VIL TDS MOSI TWL TDH VIH VIL TOV MISO VOH VOL TOH TCHZ HI-Z HI-Z Figure 23. SPI Timing Symbol Min Max 80/33.
5.5.5 Transformer Characteristics Parameter Transmit End Receive End Turn Ratio 1:1 1:1 Inductance 350 uH 350 uH Figure 24. Transformer Type 5.5.6 MDIX W5500 does not support auto-MDIX feature. Thus, user should use straight-through cables to connect to other switches or routers and crossover cables to connect to devices such as servers, workstations or another W5500.
IR Reflow Temperature Profile (Lead-Free) Moisture Sensitivity Level : 3 Dry Pack Required: Yes Average Ramp-Up Rate 3° C/second max. (Tsmax to Tp) Preheat – Temperature Min (Tsmin) 150 °C – Temperature Max (Tsmax) 200 °C – Time (tsmin to tsmax) 60-120 seconds Time maintained above: – Temperature (TL) 217 °C – Time (tL) 60-150 seconds Peak/Classification Temperature (Tp) 265 + 0/-5°C Time within 5 °C of actual Peak Temperature (tp) 30 seconds Ramp-Down Rate 6 °C/second max.
Package Descriptions Note 1. These dimensions do not include mold protrusion. 2. ( ) is reference. 3. [ ] is ass’y out quality. 4. UNIT: mm Figure 26. Package Dimensions 64 / 66 W5500 Datasheet Version1.0.
Document History Information Version Date Ver. 1.0.0 1AUG2013 Descriptions Initial Release Corrected duplicated statements and typing errors (P.14, 23, 24, 28, Ver. 1.0.1 13SEP2013 39, 51) Corrected descriptions (P.35) 1. Ver. 1.0.2 14NOV2013 Changed “descriptions of pin at 1.1 Pin Descriptions”(P.10) from It must be tied to GND to NC(PIN38~42) 2. Corrected typing error : from 0x02 to 0x42 value of SOCK_MACRAW at 4.2 Socket Registers(P.50) Ver. 1.0.3 29MAY2014 Ver. 1.0.4 13JUN2014 1.
3. Added Maximum junction temperature TJMAX (P.58) Copyright Notice Copyright 2013 WIZnet Co., Ltd. All Rights Reserved. Technical Support: support@wiznet.co.kr Sales & Distribution: sales@wiznet.co.kr For more information, visit our website at http://www.wiznet.co.kr 66 / 66 W5500 Datasheet Version1.0.
