SP3485 datasheet

5
10/15/02 SP3481/3485 Low Power Half-Duplex RS485 Transceivers © Copyright 2002 Sipex Corporation
INPUTS OUTPUTS
LINE
RE DE DI CONDITION B A
X11No Fault 0 1
X10No Fault 1 0
X0X X ZZ
INPUTS OUTPUTS
RE DE A - B R
00 +0.2V 1
00 -0.2V 0
00Inputs Open 1
10 X Z
Table 1. Transmit Function Truth Table
Table 2. Receive Function Truth Table
Figure 2. Driver Propagation Delay Test Circuit
Figure 4. Driver Enable and Disable Timing Circuit,
Output HIGH
Figure 1. Driver DC Test Load Circuit
Figure 6. Receiver Propagation Delay Test Circuit
Figure 7. Receiver Enable and Disable Timing Circuit
R
R
V
OC
D
V
CC
VOD
GENERATOR
(NOTE 1)
50Ω
V
CC
S1
V
DM
R L = 27Ω
OUT
C
L = 15pF
(NOTE 2)
V
OM = 1.5V
V OH + V OL
2
D
GENERATOR
(NOTE 1)
50Ω
S1
R
L = 110Ω
OUT
C
L = 50pF
(NOTE 2)
V
OM = 1.5V
V OH + V OL
2
D
GENERATOR
(NOTE 1)
50Ω
S1
R
L = 110Ω
OUT
C
L = 50pF
(NOTE 2)
D
0V OR 3V
V CC
GENERATOR
(NOTE 1)
50Ω
1.5V
0V
V
ID
R
OUT
C
L = 15pF
(NOTE 2)
V
OM = VCC
2
1.5V
-1.5V
S3
V
ID
GENERATOR
(NOTE 1)
50Ω
C
L = 15pF
(NOTE 2)
R
1k
S1
S2
V
CC
Figure 5. Driver Enable and Disable Timing Circuit,
Output LOW
GENERATOR
(NOTE 1)
50Ω
CL
OUT
D
VCC
RL =
60Ω
C
L = 15pF (NOTE 2)
Figure 3. Driver Differential Output Delay and Transition
Time Circuit