Data Sheet

MPU-9250 Product Specification
Document Number: PS-MPU-9250A-01
Revision: 1.0
Release Date: 01/17/2014
3.6 SPI Timing Characterization
Typical Operating Circuit of section 4.2
, VDD = 2.4V to 3.6V, VDDIO = 1.71V to VDD, T
A
=25°C, unless
otherwise noted.
Parameters
Conditions
Min
Typical
Max
Units
Note s
SPI TIMING
f
SCLK
, SCLK Clock Frequency 1 MHz
t
LOW
, SCLK Low Period 400 ns
t
HIGH
, SCLK High Period
400
ns
t
SU.CS
, CS Setup Time
8
ns
t
HD.CS
, CS Hold Time
500
ns
t
SU.SDI
, SDI Setup Time
11
ns
t
HD.SDI
, SDI Hold Time
7
ns
t
VD.SDO
, SDO Valid Time C
load
= 20pF 100 ns
t
HD.SDO
, SDO Hold Time C
load
= 20pF 4 ns
t
DIS.SDO
, SDO Output Disable Time
50
ns
Table 7 SPI Timing Characteristics
Notes:
1. Based on characterization of 5 parts over temperature and voltage as mounted on evaluation board or in sockets
SPI Bus Timing Diagram
3.6.1 fSCLK = 20MHz
Parameters
Conditions
Min
Typical
Max
Units
SPI TIMING
f
SCLK
, SCLK Clock Frequency
0.9
20
MHz
t
LOW
, SCLK Low Period - - ns
t
HIGH
, SCLK High Period - - ns
t
SU.CS
, CS Setup Time
1
ns
t
HD.CS
, CS Hold Time 1 ns
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