Data Sheet

995
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181G–SAM-D21_Datasheet–09/2015
3. See “I/O Pin Characteristics” on page 950.
Table 36-64.I2S Timing Characteristics and Requirements (Device Variant B)
Name Description Mode
V
DD
=1.8V V
DD
=3.3V
UnitsMin. Typ. Max. Min. Typ. Max.
t
M_MCKOR
I2S MCK rise time
(3)
Master mode / Capacitive load
CL = 15 pF
9.2 4.7 ns
t
M_MCKOF
I2S MCK fall time
(3)
Master mode / Capacitive load
CL = 15 pF
11.6 5.4 ns
d
M_MCKO
I2S MCK duty cycle Master mode 47.1 50.0 47.3 50.0 %
d
M_MCKI
I2S MCK duty cycle Master mode, pin is input (1b) 50.0 50.0 %
t
M_SCKOR
I2S SCK rise time
(3)
Master mode / Capacitive load
CL = 15 pF
9.0 4.6 ns
t
M_SCKOF
I2S SCK fall time
(3)
Master mode / Capacitive load
CL = 15 pF
9.7 4.6 ns
d
M_SCKO
I2S SCK duty cycle Master mode 47.0 50.0 47.2 50.0 %
f
M_SCKO
1/t
M_SCKO
I2S SCK frequency
Master mode
Supposing external device
response delay is 30ns
7.8 9.2 MHz
f
S_SCKI
1/t
S_SCKI
I2S SCK frequency
Slave mode
Supposing external device
response delay
is 30ns
12.8 13.0 MHz
d
S_SCKO
I2S SCK duty cycle Slave mode 50.0 50.0 %
t
M_FSOV
FS valid time Master mode 2.4 1.9 ns
t
M_FSOH
FS hold time Master mode -0.1 -0.1 ns
t
S_FSIS
FS setup time Slave mode 6.0 5.3 ns
t
S_FSIH
FS hold time Slave mode 0.0 0.0 ns
t
M_SDIS
Data input setup time Master mode 36.0 25.9 ns
t
M_SDIH
Data input hold time Master mode -8.2 -8.2 ns