Data Sheet

955
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181G–SAM-D21_Datasheet–09/2015
36.9.4 Analog-to-Digital (ADC) Characteristics
Notes: 1. These values are based on characterization. These values are not covered by test limits in production.
2. These values are based on simulation. These values are not covered by test limits in production or
characterization.
3. In this condition and for a sample rate of 350ksps, 1 Conversion at gain 1x takes 6 clock cycles of the ADC
clock.
Table 36-21. Operating Conditions
Symbol Parameter Conditions Min. Typ. Max. Units
RES Resolution
I
8 - 12 bits
f
CLK_ADC
ADC Clock frequency
I
30 - 2100 kHz
Conversion speed 10 1000 ksps
Sample rate
(1)
Single shot 5 - 300 ksps
Free running 5 - 350 ksps
Sampling time
(1)
0.5 - - cycles
Conversion time
(1)
1x Gain 6 - - cycles
V
REF
Voltage reference range 1.0 - V
DDANA
-0.6 V
V
REFINT1V
Internal 1V reference
(2)
- 1.0 - V
V
REFINTVCC0
Internal ratiometric
reference 0
(2)
- V
DDANA
/1.48 - V
V
REFINTVCC0
Voltage Error
Internal ratiometric
reference 0
(2)
error
2.0V <
V
DDANA
<3.63V
-1.0 - +1.0 %
V
REFINTVCC1
Internal ratiometric
reference 1
(2)
V
DDANA
>2.0V - V
DDANA
/2 - V
V
REFINTVCC1
Voltage Error
Internal ratiometric
reference 1
(2)
error
2.0V <
V
DDANA
<3.63V
-1.0 - +1.0 %
Conversion range
(1)
Differential mode -V
REF
/GAIN - +V
REF
/GAIN V
Single-ended mode 0.0 - +V
REF
/GAIN V
C
SAMPLE
Sampling capacitance
(2)
- 3.5 - pF
R
SAMPLE
Input channel source
resistance
(2)
- - 3.5 kΩ
I
DD
DC supply current
(1)
f
CLK_ADC
= 2.1MHz I
(3)
- 1.25 1.79 mA