Data Sheet

93
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181G–SAM-D21_Datasheet–09/2015
13.5 On-demand, Clock Requests
Figure 13-4. Clock request routing
All the clock sources in the system can be run in an on-demand mode, where the clock source is in a stopped state when
no peripherals are requesting the clock source. Clock requests propagate from the peripheral, via the GCLK, to the clock
source. If one or more peripheral is using a clock source, the clock source will be started/kept running. As soon as the
clock source is no longer needed and no peripheral have an active request the clock source will be stopped until
requested again. For the clock request to reach the clock source, the peripheral, the generic clock and the clock from the
Generic Clock Generator in-between must be enabled. The time taken from a clock request being asserted to the clock
source being ready is dependent on the clock source startup time, clock source frequency as well as the divider used in
the Generic Clock Generator. The total startup time from a clock request to the clock is available for the peripheral is:
Delay_start_max = Clock source startup time + 2 * clock source periods + 2 * divided clock source periods
Delay_start_min = Clock source startup time + 1 * clock source period + 1 * divided clock source period
The delay for shutting down the clock source when there is no longer an active request is:
Delay_stop_min = 1 * divided clock source period + 1 * clock source period
Delay_stop_max = 2 * divided clock source periods + 2 * clock source periods
The On-Demand principle can be disabled individually for each clock source by clearing the ONDEMAND bit located in
each clock source controller. The clock is always running whatever is the clock request. This has the effect to remove the
clock source startup time at the cost of the power consumption.
In standby mode, the clock request mechanism is still working if the modules are configured to run in standby mode
(RUNSTDBY bit).
13.6 Power Consumption vs Speed
Due to the nature of the asynchronous clocking of the peripherals there are some considerations that needs to be taken
if either targeting a low-power or a fast-acting system. If clocking a peripheral with a very low clock, the active power
consumption of the peripheral will be lower. At the same time the synchronization to the synchronous (CPU) clock
domain is dependent on the peripheral clock speed, and will be longer with a slower peripheral clock; giving lower
response time and more time waiting for the synchronization to complete.
13.7 Clocks after Reset
On any reset the synchronous clocks start to their initial state:
z OSC8M is enabled and divided by 8
z GCLK_MAIN uses OSC8M as source
z CPU and BUS clocks are undivided
On a power reset the GCLK starts to their initial state:
z All generic clock generators disabled except:
z the generator 0 (GCLK_MAIN) using OSC8M as source, with no division
z the generator 2 using OSCULP32K as source, with no division
DFLL48M
G
eneric
C
lock
G
enerator
Clock request
G
eneric
C
lock
M
ulti
p
lexer
Clock request
P
er
iph
era
l
Clock request
ENABLE
RUNSTDBY
ONDEMAND
CLKEN
RUNSTDBY
ENABLE
RUNSTDBY
GENEN