Data Sheet

925
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181G–SAM-D21_Datasheet–09/2015
34.8.5 Interrupt Enable Set
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register
will also be reflected in the Interrupt Enable Clear register (INTENCLR).
Name: INTENSET
Offset: 0x5
Reset: 0x00
Property: Write-Protected
z Bits 7:3 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z Bit 2 – SYNCRDY: Synchronization Ready Interrupt Enable
0: The Synchronization Ready interrupt is disabled.
1: The Synchronization Ready interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Synchronization Ready Interrupt Enable bit, which enables the Synchronization
Ready interrupt.
z Bit 1 – EMPTY: Data Buffer Empty Interrupt Enable
0: The Data Buffer Empty interrupt is disabled.
1: The Data Buffer Empty interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Data Buffer Empty Interrupt Enable bit, which enables the Data Buffer Empty
interrupt.
z Bit 0 – UNDERRUN: Underrun Interrupt Enable
0: The Underrun interrupt is disabled.
1: The Underrun interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Underrun Interrupt Enable bit, which enables the Underrun interrupt.
Bit 76543210
SYNCRDY EMPTY UNDERRUN
AccessRRRRRR/WR/WR/W
Reset00000000