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Data Sheet

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918
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181G–SAM-D21_Datasheet–09/2015
If an operation that requires synchronization is executed while STATUS.SYNCBUSY is one, the bus will be stalled. All
operations will complete successfully, but the CPU will be stalled and interrupts will be pending as long as the bus is
stalled.
The following bits need synchronization when written:
z Software Reset bit in the Control A register (CTRLA.SWRST)
z Enable bit in the Control A register (CTRLA.ENABLE)
z All bits in the Data register (DATA)
z All bits in the Data Buffer register (DATABUF)
Synchronization is denoted by the Write-Synchronized property in the register description.
The following bits need synchronization when read:
z All bits in the Data register (DATA)