Data Sheet

917
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181G–SAM-D21_Datasheet–09/2015
34.6.4.2 Interrupts
The DAC has the following interrupt sources:
z Data Buffer Empty (EMPTY): this asynchronous interrupt can be used to wake-up the device from any sleep mode.
z Underrun (UNDERRUN): this asynchronous interrupt can be used to wake-up the device from any sleep mode.
z Synchronization Ready (SYNCRDY): this asynchronous interrupt can be used to wake-up the device from any
sleep mode.
Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status and Clear
register (INTFLAG) is set when the interrupt condition occurs. Each interrupt can be individually enabled by writing a one
to the corresponding bit in the Interrupt Enable Set register (INTENSET), and disabled by writing a one to the
corresponding bit in the Interrupt Enable Clear register (INTENCLR). An interrupt request is generated when the interrupt
flag is set and the corresponding interrupt is enabled. The interrupt request remains active until the interrupt flag is
cleared, the interrupt is disabled or the DAC is reset. See the register description for details on how to clear interrupt
flags.
The DAC has one common interrupt request line for all the interrupt sources. The user must read the INTFLAG register
to determine which interrupt condition is present.
Note that interrupts must be globally enabled for interrupt requests to be generated. Refer to “Nested Vector Interrupt
Controller” on page 34 for details.
34.6.4.3 Events
The DAC can generate the following output events:
z Data Buffer Empty (EMPTY)
Writing a one to an Event Output bit in the Event Control register (EVCTRL.xxEO) enables the corresponding output
event. Writing a zero to this bit disables the corresponding output event. Refer to “EVSYS – Event System” on page 406
for details on configuring the event system.
The DAC can take the following actions on an input event:
z Start Conversion (START)
Writing a one to an Event Input bit in the Event Control register (EVCTRL.xxEI) enables the corresponding action on an
input event. Writing a zero to this bit disables the corresponding action on input event. Note that if several events are
connected to the DAC, the enabled action will be taken on any of the incoming events. Refer to “EVSYS – Event System”
on page 406 for details on configuring the event system.
34.6.5 Sleep Mode Operation
The generic clock for the DAC is running in idle sleep mode. If the Run In Standby bit in the Control A register
(CTRLA.RUNSTDBY) is one, the DAC output buffer will keep its value in standby sleep mode. If CTRLA.RUNSTDBY is
zero, the DAC output buffer will be disabled in standby sleep mode.
34.6.6 Synchronization
Due to the asynchronicity between CLK_DAC_APB and GCLK_DAC, some registers must be synchronized when
accessed. A register can require:
z Synchronization when written
z Synchronization when read
z Synchronization when written and read
z No synchronization
When executing an operation that requires synchronization, the Synchronization Busy bit in the Status register
(STATUS.SYNCBUSY) will be set immediately, and cleared when synchronization is complete. The Synchronization
Ready interrupt can be used to signal when synchronization is complete.