Data Sheet

863

Atmel | SMART SAM D21 [DATASHEET]

Atmel-42181G–SAM-D21_Datasheet–09/2015

32.8.4 Sampling Time Control

Name: SAMPCTRL

Offset: 0x03

Reset: 0x00

Property: Write-Protected

z Bits 7:6 – Reserved

These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to

zero when this register is written. These bits will always return zero when read.

z Bits 5:0 – SAMPLEN[5:0]: Sampling Time Length

These bits control the ADC sampling time in number of half CLK_ADC cycles, depending of the prescaler value,

thus controlling the ADC input impedance. Sampling time is set according to the equation:

Bit 76543210

SAMPLEN[5:0]

Access R R R/W R/W R/W R/W R/W R/W

Reset00000000

Sampling time SAMPLEN 1+()

CLK

ADC

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