Data Sheet

856
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181G–SAM-D21_Datasheet–09/2015
z Synchronization when read
z Synchronization when written and read
z No synchronization
When executing an operation that requires synchronization, the Synchronization Busy bit in the Status register
(STATUS.SYNCBUSY) will be set immediately, and cleared when synchronization is complete. The Synchronization
Ready interrupt can be used to signal when synchronization is complete.
If an operation that requires synchronization is executed while STATUS.SYNCBUSY is one, the bus will be stalled. All
operations will complete successfully, but the CPU will be stalled and interrupts will be pending as long as the bus is
stalled.
The following bits need synchronization when written:
z Software Reset bit in the Control A register (CTRLA.SWRST)
z Enable bit in the Control A register (CTRLA.ENABLE)
The following registers need synchronization when written:
z Control B (CTRLB)
z Software Trigger (SWTRIG)
z Window Monitor Control (WINCTRL)
z Input Control (INPUTCTRL)
z Window Upper/Lower Threshold (WINUT/WINLT)
Write-synchronization is denoted by the Write-Synchronized property in the register description.
The following registers need synchronization when read:
z Software Trigger (SWTRIG)
z Input Control (INPUTCTRL)
z Result (RESULT)
Read-synchronization is denoted by the Read-Synchronized property in the register description.