Data Sheet

854
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181G–SAM-D21_Datasheet–09/2015
In single conversion, a latency of 13 GCLK_ADC is added to the availability of the final result. Since the correction time is
always less than the propagation delay, this latency appears in free-running mode only during the first conversion. After
that, a new conversion will be initialized when a conversion completes. All other conversion results are available at the
defined sampling rate.
Figure 32-8. ADC Timing Correction Enabled
32.6.11 DMA, Interrupts and Events
32.6.11.1 DMA Operation
The ADC generates the following DMA request:
z Result Conversion Ready (RESRDY): the request is set when a conversion result is available and cleared when
the RESULT register is read. When the averaging operation is enabled, the DMA request is set when the
averaging is completed and result is available.
32.6.11.2 Interrupts
The ADC has the following interrupt sources:
Result Conversion value OFFSETCORR–()GAINCORR⋅=
START
CONV0 CONV1 CONV2 CONV3
CORR0 CORR1 CORR2 CORR3
Table 32-5. Module Request for ADC
Condition Interrupt request Event output Event input DMA request
DMA request is
cleared
Result Ready x x x
When result
register is read
Overrun x
Window Monitor x x
Synchronization
Ready
x
Start Conversion x
ADC Flush x