Data Sheet

851
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181G–SAM-D21_Datasheet–09/2015
Figure 32-6. ADC Timing for One Conversion in Single-Ended Mode without Gain
Figure 32-7. ADC Timing for Free Running in Single-Ended Mode without Gain
32.6.6 Accumulation
The result from multiple consecutive conversions can be accumulated. The number of samples to be accumulated is
specified by writing to the Number of Samples to be Collected field in the Average Control register
(AVGCTRL.SAMPLENUM) as described in Table 32-2. When accumulating more than 16 samples, the result will be too
large for the 16-bit RESULT register. To avoid overflow, the result is shifted right automatically to fit within the 16
available bits. The number of automatic right shifts are specified in Table 32-2. Note that to be able to perform the
accumulation of two or more samples, the Conversion Result Resolution field in the Control B register (CTRLB.RESSEL)
must be written to one.
Table 32-2. Accumulation
12345678
CLK_ADC
START
SAMPLE
INT
Conver ting Bit
91011
AMPLIFY
MSB10987654321LSB
1
2345678
CLK_ ADC
START
SAMPLE
INT
Converting Bit
9101112 13 14 15 16
11109876543210 11 109876543210 1110
AMPLIFY
Number of
Accumulated Samples
AVGCTRL.
SAMPLENUM
Intermediate
Result Precision
Number of Automatic
Right Shifts
Final Result
Precision
Automatic
Division Factor
1 0x0 12 bits 0 12 bits 0
2 0x1 13 bits 0 13 bits 0
4 0x2 14 bits 0 14 bits 0