Data Sheet

848
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181G–SAM-D21_Datasheet–09/2015
32.6.3 Prescaler
The ADC is clocked by GCLK_ADC. There is also a prescaler in the ADC to enable conversion at lower clock rates.
Refer to CTRLB for details on prescaler settings.
Figure 32-2. ADC Prescaler
The propagation delay of an ADC measurement depends on the selected mode and is given by:
z Single-shot mode:
z Free-running mode:
GCLK_ADC 9-BIT PRESCALER
CTRLB.PRESCALER[2:0]
DIV512
DIV256
DIV128
DIV64
DIV32
DIV16
DIV8
DIV4
CLK_ADC
PropagationDelay
1
Resolution
2
----------------------------
DelayGain++
f
CLK ADC–
--------------------------------------------------------------------------
=
PropagationDelay
Resolution
2
----------------------------
DelayGain+
f
CLK ADC–
----------------------------------------------------------------
=