Data Sheet

832
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181G–SAM-D21_Datasheet–09/2015
z Bit 1 – TRCPT1: Transfer Complete Bank 1 interrupt Enable
0: The Transfer Complete Bank 1 interrupt is disabled.
1: The Transfer Complete Bank 1 interrupt is enabled and an interrupt request will be generated when the Transfer
Complete interrupt Flag 1 is set.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Transfer Complete interrupt Enable bit 1 and disable the corresponding inter-
rupt request.
z Bit 0 – TRCPT0: Transfer Complete Bank 0 interrupt Enable
0: The Transfer Complete Bank 0 interrupt is disabled.
1: The Transfer Complete Bank 0 interrupt is enabled and an interrupt request will be generated when the Transfer
Complete interrupt 0 Flag is set.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Transfer Complete interrupt Enable bit 0 and disable the corresponding inter-
rupt request.