Data Sheet

811
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181G–SAM-D21_Datasheet–09/2015
31.8.5.2 Host Start-of-Frame Control Register
Name:
HSOFC
Offset: 0x0A
Reset: 0x0000
Property: Write-Protected
During a very short period just before transmitting a Start-of-Frame, this register is locked.Thus, after writing, it is
recommended to check the register value, and write this register again if necessary. This register is cleared upon
a USB reset.
z Bit 7 – FLENCE: Frame Length Control Enable
0: The internal frame length down counter is loaded with default value as shown below in the table.
1: The internal frame length down counter is loaded with FLENC[3:0] value at the beginning of a frame.
z Bits 3:0 – FLENC: Frame Length Control
These bits define the signed value of the 4-bit FLENC that is added to the Internal Frame Length when FLENCE is
one.The internal Frame length is the top value of the frame counter when FLENCE is zero.
Bit76543210
FLENCE FLENC[3:0]
Access R/W R R R R/W R/W R/W R/W
Reset00000000
Table 31-19. Internal Frame Length Down-Counter
FLENCE Frame Timing Internal Frame Length Down-Counter Load Value
0
Internal Frame Length
(Low Speed, Full Speed)
11999 (gives 1 ms frame rate at 12Mhz)
1
Beginning of Frame FLENC[3:0]
Internal Frame Length with
Frame correction
The signed value from FLENC[3:0] is added to the internal Frame
length (see FLENCE = 0) at all speeds.