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Atmel | SMART SAM D21 [DATASHEET]

Atmel-42181G–SAM-D21_Datasheet–09/2015

31.8.3.7 Device Interrupt EndPoint Set

Name:

EPINTENSET

Offset: 0x109 + (n x 0x20)

Reset: 0x0000

Property: Write-Protected

This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this

register will also be reflected in the Endpoint Interrupt Enable Set (EPINTENCLR) register.

This register is cleared by USB reset or when EPEN[n] is zero.

z Bits 7 – Reserved

This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero

when this register is written. This bit will always return zero when read.

z Bit 6 – STALL1: Transmit Stall 1 Interrupt Enable

0: The Transmit Stall 1 interrupt is disabled.

1: The Transmit Stall 1 interrupt is enabled.

Writing a zero to this bit has no effect.

Writing a one to this bit will enable the Transmit bank 1 Stall interrupt.

z Bit 5 – STALL0: Transmit Stall 0 Interrupt Enable

0: The Transmit Stall 0 interrupt is disabled.

1: The Transmit Stall 0 interrupt is enabled.

Writing a zero to this bit has no effect.

Writing a one to this bit will enable the Transmit bank 0 Stall interrupt.

z Bit 4 – RXSTP: Received Setup Interrupt Enable

0: The Received Setup interrupt is disabled.

1: The Received Setup interrupt is enabled.

Writing a zero to this bit has no effect.

Writing a one to this bit will enable the Received Setup interrupt.

z Bit 3 – TRFAIL1: Transfer Fail bank 1 Interrupt Enable

0: The Transfer Fail interrupt is disabled.

1: The Transfer Fail interrupt is enabled.

Writing a zero to this bit has no effect.

Writing a one to this bit will enable the Transfer Fail interrupt.

z Bit 3 – TRFAIL0: Transfer Fail bank 0 Interrupt Enable

0: The Transfer Fail interrupt is disabled.

1: The Transfer Fail interrupt is enabled.

Writing a zero to this bit has no effect.

Writing a one to this bit will enable the Transfer Fail interrupt.

Bit76543210

STALL1 STALL0 RXSTP TRFAIL1 TRFAIL0 TRCPT1 TRCPT0

Access R R/W R/W R/W R/W R/W R/W R/W

Reset00000000