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Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181G–SAM-D21_Datasheet–09/2015
31.8.3.6 Device EndPoint Interrupt Enable
Name:
EPINTENCLR
Offset: 0x108 + (n x 0x20)
Reset: 0x00
Property: Write-Protected
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Endpoint Interrupt Enable Set (EPINTENSET) register.
This register is cleared by USB reset or when EPEN[n] is zero.
z Bits 7 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
z Bit 6 – STALL1: Transmit STALL 1 Interrupt Enable
0: The Transmit Stall 1 interrupt is disabled.
1: The Transmit Stall 1 interrupt is enabled and an interrupt request will be generated when the Transmit Stall 1
Interrupt Flag is set.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Transmit Stall 1 Interrupt Enable bit and disable the corresponding interrupt
request.
z Bit 5 – STALL0: Transmit STALL 0 Interrupt Enable
0: The Transmit Stall 0 interrupt is disabled.
1: The Transmit Stall 0 interrupt is enabled and an interrupt request will be generated when the Transmit Stall 0
Interrupt Flag is set.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Transmit Stall 0 Interrupt Enable bit and disable the corresponding interrupt
request.
z Bit 4 – RXSTP: Received Setup Interrupt Enable
0: The Received Setup interrupt is disabled.
1: The Received Setup interrupt is enabled and an interrupt request will be generated when the Received Setup
Interrupt Flag is set.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Received Setup Interrupt Enable bit and disable the corresponding interrupt
request.
z Bit 3 – TRFAIL1: Transfer Fail 1 Interrupt Enable
0: The Transfer Fail 1 interrupt is disabled.
1: The Transfer Fail 1 interrupt is enabled and an interrupt request will be generated when the Transfer Fail 1 Inter-
rupt Flag is set.
Bit76543210
STALL1 STALL0 RXSTP TRFAIL1 TRFAIL0 TRCPT1 TRCPT0
Access R R/W R/W R/W R/W R/W R/W R/W
Reset00000000