Data Sheet

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Atmel | SMART SAM D21 [DATASHEET]

Atmel-42181G–SAM-D21_Datasheet–09/2015

31.8.2.6 Device Interrupt Enable Set

This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register

will also be reflected in the Interrupt Enable Clear (INTENCLR) register.

Name: INTENSET

Offset: 0x18

Reset: 0x0000

Property: Write-Protected

z Bits 15:10 – Reserved

These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to

zero when this register is written. These bits will always return zero when read.

z Bit 9 – LPMSUSP: Link Power Management Suspend Interrupt Enable

0: The Link Power Management Suspend interrupt is disabled.

1: The Link Power Management Suspend interrupt is enabled.

Writing a zero to this bit has no effect.

Writing a one to this bit will set the Link Power Management Suspend Enable bit and enable the corresponding

interrupt request.

z Bit 8 – LPMNYET: Link Power Management Not Yet Interrupt Enable

0: The Link Power Management Not Yet interrupt is disabled.

1: The Link Power Management Not Yet interrupt is enabled.

Writing a zero to this bit has no effect.

Writing a one to this bit will set the Link Power Management Not Yet interrupt bit and enable the corresponding

interrupt request.

z Bit 7 – RAMACER: RAM Access Interrupt Enable

0: The RAM Access interrupt is disabled.

1: The RAM Access interrupt is enabled.

Writing a zero to this bit has no effect.

Writing a one to this bit will set the RAM Access Enable bit and enable the corresponding interrupt request.

z Bit 6 – UPRSM: Upstream Resume Interrupt Enable

0: The Upstream Resume interrupt is disabled.

1: The Upstream Resume interrupt is enabled.

Writing a zero to this bit has no effect.

Writing a one to this bit will set the Upstream Resume Enable bit and enable the corresponding interrupt request.

z Bit 5 – EORSM: End Of Resume Interrupt Enable

0: The End Of Resume interrupt is disabled.

Bit151413121110 9 8

LPMSUSP LPMNYET

AccessRRRRRRR/WR/W

Reset00000000

Bit76543210

RAMACER UPRSM EORSM WAKEUP EORST SOF SUSPEND

Access R/W R/W R/W R/W R/W R/W R R/W

Reset00000000