Data Sheet

31.7 Register Summary
The register mapping depends on the Operating Mode field in the Control A register (CTRLA.MODE). The
register summary is detailed below.
31.7.1 Common Device Host Summary
Table 31-1. Common Register Summary
31.7.2 Device Summary
Table 31-2. General Device Registers Summary
Offset Name
Bit
Pos.
0x00 CTRLA 7:0 MODE RUNSTBY ENABLE SWRST
0x01 Reserved
0x02 SYNCBUSY 7:0 ENABLE SWRST
0x03 QOSCTRL 7:0 DQOS[1:0] CQOS[1:0]
0x0D FSMSTATUS 7:0 FSMSTATE[6:0]
0x24
DESCADD
7:0 DESCADD[7:0]
0x25 15:8 DESCADD[15:8]
0x26 23:16 DESCADD[23:16]
0x27 31:24 DESCADD[31:24]
0x28
PADCAL
7:0 TRANSN[1:0] TRANSP[4:0]
0x29 15:8 TRIM[2:0] TRANSN[4:2]
Offset Name
Bit
Pos.
0x04 Reserved
0x05 Reserved
0x06 Reserved
0x07 Reserved
0x08
CTRLB
7:0 NREPLY SPDCONF[1:0] UPRSM DETACH
0x09 15:8 LPMHDSK[1:0] GNAK
0x0A DADD ADDEN DADD[6:0]
0x0B Reserved
0x0C STATUS 7:0 LINESTATE[1:0] SPEED[1:0]
0x0E Reserved
0x0F Reserved
0x10
FNUM
7:0 FNUM[4:0]
0x11 15:8 FNCERR FNUM[10:5]
0x12 Reserved
0x14
INTENCLR
7:0 RAMACER UPRSM EORSM WAKEUP EORST SOF SUSPEND
0x15 15:8 LPMSUSP LPMNYET
0x16 Reserved
0x17 Reserved