Data Sheet

746
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181G–SAM-D21_Datasheet–09/2015
31.5.2 Power Management
The USB will continue to operate in any sleep mode where the selected source clock is running. The USB’s interrupts can be
used to wake up the device from sleep modes. Events connected to the event system can trigger other operations in the system
without exiting sleep modes. Refer to the “PM – Power Manager” on page 117 for details on the different sleep modes.
31.5.3 Clocks
The USB bus clock (CLK_USB_AHB) can be enabled and disabled in the Power Manager, and the default state of
CLK_USB_AHB can be found in the Peripheral Clock Masking section in “PM – Power Manager” on page 117.
A generic clock (GCLK_USB) is required to clock the USB. This clock must be configured and enabled in the Generic
Clock Controller before using the USB. Refer to “GCLK – Generic Clock Controller” on page 95 for further details.
This generic clock is asynchronous to the bus clock (CLK_USB_AHB). Due to this asynchronicity, writes to certain
registers will require synchronization between the clock domains. Refer to “Synchronization” on page 101 for further
details.
The USB module requires a GCLK_USB of 48 MHz ± 0.25% clock for low speed and full speed operation. To follow the
USB data rate at 12Mbit/s in full-speed mode, the CLK_USB_AHB clock should be at minimum 8MHz.
Clock recovery is achieved by a digital phase-locked loop in the USB module, which complies with the USB jitter
specifications. If crystal-less operation is used in USB device mode, please refer to “USB Clock Recovery Mode” on page
157.
31.5.4 DMA
The USB has a built-in Direct Memory Access (DMA) and will read/write data from/to the system RAM when a USB
transaction takes place. No CPU or DMA Controller resources are required.
31.5.5 Interrupts
The interrupt request lines are connected to the interrupt controller. Using the USB interrupts requires the interrupt controller to
be configured first.
Refer to “Nested Vector Interrupt Controller” on page 34 for details.
31.5.6 Events
Not Applicable
31.5.7 Debug Operation
When the CPU is halted in debug mode the USB continues normal operation. If the USB is configured in a way that
requires it to be periodically serviced by the CPU through interrupts or similar, improper operation or data loss may result
during debugging.
31.5.8 Register Access Protection
All registers with write-access are optionally write-protected by the peripheral access controller (PAC), except the
following registers:
z Device Interrupt Flag (INTFLAG) register
z Endpoint Interrupt Flag (EPINTFLAG) register
z Host Interrupt Flag (INTFLAG) register
z Pipe Interrupt Flag (PINTFLAG) register
Write-protection is denoted by the Write-Protected property in the register description.
Write-protection does not apply to accesses through an external debugger. Refer to “PAC – Peripheral Access
Controller” on page 41 for details.