Data Sheet

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Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181G–SAM-D21_Datasheet–09/2015
z Bits 11:8 – CICCENBx [x=3..0]: Circular Channel x Enable Buffer
These bits represent the CICCEN buffers. When the double buffering is enable, CICCENB bits value is copied to
the CICCEN bits on an UPDATE condition.
z Bit 7 – CIPERENB: Circular Period Enable Buffer
This bit represents the CIPEREN buffer. When the double buffering is enable, CIPERENB bit value is copied to the
CIPEREN bit on an UPDATE condition.
z Bit 6 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
z Bits 5:4 – RAMPB[1:0]: Ramp Mode Buffer
These bits represent the RAMP buffers. When the double buffering is enable, RAMPB bits value is copied to the
RAMP bits on an UPDATE condition.
Table 30-28. Ramp Mode Buffer
z Bit 3 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
z Bits 2:0 – WAVEGENB[2:0]: Waveform Generation Buffer
These bits represent the WAVEGEN buffers. When the double buffering is enable, WAVEGENB bits value is cop-
ied to the WAVEGEN bits on an UPDATE condition.
Table 30-29. Waveform Generation Buffer
RAMPB[1:0] Name Description
0x0 RAMP1 RAMP1 operation
0x1 RAMP2A Alternative RAMP2 operation
0x2 RAMP2 RAMP2 operation
0x3 Reserved
WAVEGENB[2:0] Name Description
0x0 NFRQ Normal frequency
0x1 MFRQ Match frequency
0x2 NPWM Normal PWM
0x3 Reserved
0x4 DSCRITICAL Dual-slope critical
0x5 DSBOTTOM
Dual-slope with interrupt/event condition when COUNT
reaches ZERO
0x6 DSBOTH
Dual-slope with interrupt/event condition when COUNT
reaches ZERO or TOP
0x7 DSTOP
Dual-slope with interrupt/event condition when COUNT
reaches TOP