Data Sheet

734
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181G–SAM-D21_Datasheet–09/2015
Mode: DITH6
Name: CCn
Offset: 0x44+n*0x4 [n=0..3]
Reset: 0x00000000
Property: -
z Bits 31:24 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z Bits 23:6 – CC[17:0]: Channel Compare/Capture Value
These bits hold the value of the Channel x compare/capture register.
The number of bits in this field corresponds to the size of the counter.
z Bits 5:0 – DITHERCY[5:0]: Dithering Cycle Number
These bits hold the number of extra cycles that are added on the PWM pulse width each number of frames as
specified in Table 30-8 on page 690.
Bit 3130292827262524
AccessRRRRRRRR
Reset00000000
Bit 2322212019181716
CC[17:10]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
Bit 151413121110 9 8
CC[9:2]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
Bit 76543210
CC[1:0] DITHERCY[5:0]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000