Data Sheet

726
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181G–SAM-D21_Datasheet–09/2015
30.8.17 Waveform Control
Name: WAVE
Offset: 0x3C
Reset: 0x00000000
Property: Write-Synchronized
z Bits 31:28 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z Bits 27:24 – SWAPx [x=3..0]: Swap DTI Output Pair x
Setting these bits enables output swap of DTI outputs [x] and [x+WO_NUM/2]. Note the DTIxEN settings will not
affect the swap operation.
z Bits 23:20 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z Bits 19:16 – POLx [x=3..0]: Channel x Polarity
Setting these bits enable the output polarity in single-slope and dual-slope PWM operations.
In single-slope PWM waveform generation:
0: Compare output is initialized to ~DIR and set to DIR when TCC counter matches CCx value
1: Compare output is initialized to DIR and set to ~DIR when TCC counter matches CCx value.
In dual-slope PWM waveform generation:
0: Compare output is set to ~DIR when TCC counter matches CCx value
Bit 3130292827262524
SWAP3 SWAP2 SWAP1 SWAP0
AccessRRRRR/WR/WR/WR/W
Reset00000000
Bit 2322212019181716
POL3 POL2 POL1 POL0
AccessRRRRR/WR/WR/WR/W
Reset00000000
Bit 151413121110 9 8
CICCEN3 CICCEN2 CICCEN1 CICCEN0
AccessRRRRR/WR/WR/WR/W
Reset00000000
Bit 76543210
CIPEREN
RAMP[1:0] WAVEGEN[2:0]
Access R/W R R/W R/W R R/W R/W R/W
Reset00000000