Data Sheet

721
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181G–SAM-D21_Datasheet–09/2015
When the bit is set, the counter is halted and the waveforms state depend on DRVCTRL.NRE and DRVCTRL.NRV
registers.
z Bit 2 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
z Bit 1 – IDX: Ramp
In RAMP2 and RAMP2A operation, the bit is cleared during the cycle A and set during the cycle B. In RAMP1
operation, the bit is always read zero. For details on ramp operations, refer to “Ramp Operations” on page 670.
z Bit 0 – STOP: Stop
This bit is set when the TCC is disabled, on a STOP command or on an UPDATE condition when One-Shot oper-
ation mode is enabled (CTRLBSET.ONESHOT = 1).
This bit is clear on the next incoming counter increment or decrement.
0: Counter is running.
1: Counter is stopped.