Data Sheet

720
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181G–SAM-D21_Datasheet–09/2015
z Bit 15 – FAULT1: Non-Recoverable Fault 1 State
This bit is set by hardware as soon as non-recoverable Fault 1 condition occurs.
This bit is cleared by writing a one to this bit and when the corresponding FAULT1IN status bit is low.
Once this bit is clear, the timer/counter will restart from the last COUNT value. To restart the timer/counter from
BOTTOM, the timer/counter restart command must be executed before clearing the corresponding FAULT1 bit.
For further details on timer/counter commands, refer to available commands description (CTRLBSET.CMD).
z Bit 14 – FAULT0: Non-Recoverable Fault 0 State
This bit is set by hardware as soon as non-recoverable Fault 0 condition occurs.
This bit is cleared by writing a one to this bit and when the corresponding FAULT0IN status bit is low.
Once this bit is clear, the timer/counter will restart from the last COUNT value. To restart the timer/counter from
BOTTOM, the timer/counter restart command must be executed before clearing the corresponding FAULT0 bit.
For further details on timer/counter commands, refer to available commands description (CTRLBSET.CMD).
z Bit 13 – FAULTB: Recoverable Fault B State
This bit is set by hardware as soon as recoverable Fault B condition occurs.
This bit is cleared by hardware when Fault B action is resumed, or by writing a one to this bit when the correspond-
ing FAULTBIN bit is low. If software halt command is enabled (FCTRLB.HALT=SW), clearing this bit release the
timer/counter.
z Bit 12 – FAULTA: Recoverable Fault A State
This bit is set by hardware as soon as recoverable Fault A condition occurs.
This bit is cleared by hardware when Fault A action is resumed, or by writing a one to this bit when the correspond-
ing FAULTAIN bit is low. If software halt command is enabled (FCTRLA.HALT=SW), clearing this bit release the
timer/counter.
z Bit 11 – FAULT1IN: Non-Recoverable Fault1 Input
This bit is set while an active Non-Recoverable Fault 1 input is present.
z Bit 10 – FAULT0IN: Non-Recoverable Fault0 Input
This bit is set while an active Non-Recoverable Fault 0 input is present.
z Bit 9 – FAULTBIN: Recoverable Fault B Input
This bit is set while an active Recoverable Fault B input is present.
z Bit 8 – FAULTAIN: Recoverable Fault A Input
This bit is set while an active Recoverable Fault A input is present.
z Bit 7 – PERBV: Period Buffer Valid
This bit is set when a new value is written to the PERB register. This bit is automatically cleared by hardware on
UPDATE condition or by writing a one to this bit.
z Bit 6 – WAVEBV: Wave Buffer Valid
This bit is set when a new value is written to the WAVEB register. This bit is automatically cleared by hardware on
UPDATE condition or by writing a one to this bit.
z Bit 5 – PATTBV: Pattern Buffer Valid
This bit is set when a new value is written to the PATTB register. This bit is automatically cleared by hardware on
UPDATE condition or by writing a one to this bit.
z Bit 4 – SLAVE: Slave
Tis bit is set when TCC is set in Slave mode. This bit follows the CTRLA.MSYNC bit state.
z Bit 3 – DFS: Non-Recoverable Debug Fault State
This bit is set by hardware in debug mode when DBGCTRL.FDDBD bit is set. The bit is cleared by writing a one to
this bit and when the TCC is not in debug mode.