Data Sheet

717
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181G–SAM-D21_Datasheet–09/2015
30.8.13 Interrupt Flag Status and Clear
Name: INTFLAG
Offset: 0x2C
Reset: 0x00000000
Property: -
z Bits 31:20 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z Bits 19:16 – MCx [x=3..0]: Match or Capture x
This flag is set on the next CLK_TCC_COUNT cycle after a match with the compare condition or once CCx regis-
ter contain a valid capture value.
Writing a zero to one of these bits has no effect.
Writing a one to one of these bits will clear the corresponding Match or Capture Channel x interrupt flag
In Capture operation, this flag is automatically cleared when CCx register is read.
z Bit 15 – FAULT1: Non-Recoverable Fault 1
This flag is set on the next CLK_TCC_COUNT cycle after a Non-Recoverable Fault 1 occurs.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the Non-Recoverable Fault 1 interrupt flag.
z Bit 14 – FAULT0: Non-Recoverable Fault 0
This flag is set on the next CLK_TCC_COUNT cycle after a Non-Recoverable Fault 0 occurs.
Writing a zero to this bit has no effect.
Bit 3130292827262524
AccessRRRRRRRR
Reset00000000
Bit 2322212019181716
MC3 MC2 MC1 MC0
AccessRRRRR/WR/WR/WR/W
Reset00000000
Bit 151413121110 9 8
FAULT1 FAULT0 FAULTB FAULTA DFS
Access R/W R/W R/W R/W R/W R R R
Reset00000000
Bit 76543210
ERR CNT TRG OVF
AccessRRRRR/WR/WR/WR/W
Reset00000000