Data Sheet

715
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181G–SAM-D21_Datasheet–09/2015
Writing a one to this bit will set the Non-Recoverable Fault 1 Interrupt Disable/Enable bit, which enables the Non-
Recoverable Fault 1 interrupt.
z Bit 14 – FAULT0: Non-Recoverable Fault 0 Interrupt Enable
0: The Non-Recoverable Fault 0 interrupt is disabled.
1: The Non-Recoverable Fault 0 interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Non-Recoverable Fault 0 Interrupt Disable/Enable bit, which enables the Non-
Recoverable Fault 0 interrupt.
z Bit 13 – FAULTB: Recoverable Fault B Interrupt Enable
0: The Recoverable Fault B interrupt is disabled.
1: The Recoverable Fault B interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Recoverable Fault B Interrupt Disable/Enable bit, which enables the Recover-
able Fault B interrupt.
z Bit 12 – FAULTA: Recoverable Fault A Interrupt Enable
0: The Recoverable Fault A interrupt is disabled.
1: The Recoverable Fault A interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Recoverable Fault A Interrupt Disable/Enable bit, which enables the Recover-
able Fault A interrupt.
z Bit 11 – DFS: Non-Recoverable Debug Fault Interrupt Enable
0: The Debug Fault State interrupt is disabled.
1: The Debug Fault State interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Debug Fault State Interrupt Disable/Enable bit, which enables the Debug Fault
State interrupt.
z Bits 10:4 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z Bit 3 – ERR: Error Interrupt Enable
0: The Error interrupt is disabled.
1: The Error interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Error Interrupt Disable/Enable bit, which enables the Error interrupt.
z Bit 2 – CNT: Counter Interrupt Enable
0: The Counter interrupt is disabled.
1: The Counter interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Retrigger Interrupt Disable/Enable bit, which enables the Counter interrupt.
z Bit 1 – TRG: Retrigger Interrupt Enable
0: The Retrigger interrupt is disabled.
1: The Retrigger interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Retrigger Interrupt Disable/Enable bit, which enables the Retrigger interrupt.