Data Sheet

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Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181G–SAM-D21_Datasheet–09/2015
30.8.12 Interrupt Enable Set
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register
will also be reflected in the Interrupt Enable Clear (INTENCLR) register.
Name: INTENSET
Offset: 0x28
Reset: 0x00000000
Property: Write-Protected
z Bits 31:20 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z Bits 19:16 – MCx [x=3..0]: Match or Capture Channel x Interrupt Enable
0: The Match or Capture Channel x interrupt is disabled.
1: The Match or Capture Channel x interrupt is enabled.
Writing a zero to MCx has no effect.
Writing a one to MCx will set the corresponding Match or Capture Channel x Interrupt Disable/Enable bit, which
enables the Match or Capture Channel x interrupt.
z Bit 15 – FAULT1: Non-Recoverable Fault 1 Interrupt Enable
0: The Non-Recoverable Fault 1 interrupt is disabled.
1: The Non-Recoverable Fault 1 interrupt is enabled.
Writing a zero to this bit has no effect.
Bit 3130292827262524
AccessRRRRRRRR
Reset00000000
Bit 2322212019181716
MC3 MC2 MC1 MC0
AccessRRRRR/WR/WR/WR/W
Reset00000000
Bit 151413121110 9 8
FAULT1 FAULT0 FAULTB FAULTA DFS
Access R/W R/W R/W R/W R/W R R R
Reset00000000
Bit 76543210
ERR CNT TRG OVF
AccessRRRRR/WR/WR/WR/W
Reset00000000