Data Sheet

703
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181G–SAM-D21_Datasheet–09/2015
30.8.7 Waveform Extension Configuration
Name: WEXCTRL
Offset: 0x14
Reset: 0x00000000
Property: Enable-Protected, Write-Protected
z Bits 31:24 – DTHS[7:0]: Dead-time High Side Outputs Value
This register holds the number of GCLK_TCC clock cycles for the dead-time high side.
z Bits 23:16 – DTLS[7:0]: Dead-time Low Side Outputs Value
This register holds the number of GCLK_TCC clock cycles for the dead-time low side.
z Bits 15:12 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z Bits 11:8 – DTIENx [x=3..0]: Dead-time Insertion Generator x Enable
Setting any of these bits enables the dead-time insertion generator for the corresponding output matrix. This will
override the output matrix [x] and [x+WO_NUM/2], with the low side and high side waveform respectively.
0: No dead-time insertion override.
1: Dead time insertion override on signal outputs[x] and [x+WO_NUM/2], from matrix outputs[x] signal.
z Bits 7:2 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
Bit 3130292827262524
DTHS[7:0]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
Bit 2322212019181716
DTLS[7:0]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
Bit 151413121110 9 8
DTIEN3 DTIEN2 DTIEN1 DTIEN0
AccessRRRRR/WR/WR/WR/W
Reset00000000
Bit 76543210
OTMX[1:0]
AccessRRRRRRR/WR/W
Reset00000000