Data Sheet
696
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181G–SAM-D21_Datasheet–09/2015
This bit is set when the synchronization of WAVEB register between clock domains is started.
z Bit 16 – PATTB: Pattern Buffer Busy
This bit is cleared when the synchronization of PATTB register between the clock domains is complete.
This bit is set when the synchronization of PATTB register between clock domains is started.
z Bits 15:12 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z Bits 11:8 – CCx [x=3..0]: Compare Channel x Busy
This bit is cleared when the synchronization of Compare/Capture Channel x register between the clock domains is
complete.
This bit is set when the synchronization of Compare/Capture Channel x register between clock domains is started.
CCx bit is available only for existing Compare/Capture Channels. For details on CC channels number, refer to
each TCC feature list.
This bit is set when the synchronization of CCx register between clock domains is started.
z Bit 7 – PER: Period busy
This bit is cleared when the synchronization of PER register between the clock domains is complete.
This bit is set when the synchronization of PER register between clock domains is started.
z Bit 6 – WAVE: Wave Busy
This bit is cleared when the synchronization of WAVE register between the clock domains is complete.
This bit is set when the synchronization of WAVE register between clock domains is started.
z Bit 5 – PATT: Pattern Busy
This bit is cleared when the synchronization of PATT register between the clock domains is complete.
This bit is set when the synchronization of PATT register between clock domains is started.
z Bit 4 – COUNT: Count Busy
This bit is cleared when the synchronization of COUNT register between the clock domains is complete.
This bit is set when the synchronization of COUNT register between clock domains is started.
z Bit 3 – STATUS: Status Busy
This bit is cleared when the synchronization of STATUS register between the clock domains is complete.
This bit is set when the synchronization of STATUS register between clock domains is started.
z Bit 2 – CTRLB: Ctrlb Busy
This bit is cleared when the synchronization of CTRLB register between the clock domains is complete.
This bit is set when the synchronization of CTRLB register between clock domains is started.
z Bit 1 – ENABLE: Enable Busy
This bit is cleared when the synchronization of ENABLE register bit between the clock domains is complete.
This bit is set when the synchronization of ENABLE register bit between clock domains is started.
z Bit 0 – SWRST: Swrst Busy
This bit is cleared when the synchronization of SWRST register bit between the clock domains is complete.
This bit is set when the synchronization of SWRST register bit between clock domains is started.