Data Sheet

695
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181G–SAM-D21_Datasheet–09/2015
30.8.4 Synchronization Busy
Name: SYNCBUSY
Offset: 0x08
Reset: 0x00000000
Property: -
z Bits 31:23 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z Bits 22:19 – CCBx [x=3..0]: Compare Channel Buffer x Busy
This bit is cleared when the synchronization of Compare/Capture Channel x Buffer register between the clock
domains is complete.
This bit is set when the synchronization of Compare/Capture Channel x Buffer register between clock domains is
started.
CCBx bit is available only for existing Compare/Capture Channels. For details on CC channels number, refer to
each TCC feature list.
This bit is set when the synchronization of CCBx register between clock domains is started.
z Bit 18 – PERB: Period Buffer Busy
This bit is cleared when the synchronization of PERB register between the clock domains is complete.
This bit is set when the synchronization of PERB register between clock domains is started.
z Bit 17 – WAVEB: Wave Buffer Busy
This bit is cleared when the synchronization of WAVEB register between the clock domains is complete.
Bit 3130292827262524
AccessRRRRRRRR
Reset00000000
Bit 2322212019181716
CCB3 CCB2 CCB1 CCB0 PERB WAVEB PATTB
AccessRRRRRRRR
Reset00000000
Bit 151413121110 9 8
CC3 CC2 CC1 CC0
AccessRRRRRRRR
Reset00000000
Bit 76543210
PER WAVE PATT COUNT STATUS CTRLB ENABLE SWRST
AccessRRRRRRRR
Reset00000000