Data Sheet

663
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181G–SAM-D21_Datasheet–09/2015
Output Polarity
The polarity (WAVE.POLx) is available in all waveform output generation. In single-slope and dual-slope PWM
generation, it is possible to invert individually the pulse edge alignment on start or end of PWM cycle for each compare
channels. Table 30-2 shows the waveform output set/clear conditions, depending on timer/counter settings, direction and
polarity setting.
In Normal and Match Frequency, the WAVE.POLx value represents the initial state of the waveform output.
30.6.2.6 Double Buffering
The Pattern (PATT), Waveform (WAVE), Period (PER) and the Compare Channels (CCx) registers are all double
buffered. Each buffer register has a Buffer Valid (PATTBV, WAVEBV, PERBV or CCBVx) bit in the STATUS register,
which indicates that the buffer register contains a value that can be copied into the corresponding register. When double
buffering is enabled by writing a one to the Lock Update bit in the Control B Clear register (CTRLBCLR.LUPD) and the
PER and CCx are used for a compare operation, the Buffer Valid bit is set when data has been written to a buffer register
and cleared on an update condition.
This is shown for a compare register in Figure 30-11.
NPWM Single-slope PWM PER TOP/ZERO
See Table 30-2
TOP ZERO
DSCRITICAL Dual-slope PWM PER ZERO - ZERO
DSBOTTOM Dual-slope PWM PER ZERO - ZERO
DSBOTH Dual-slope PWM PER TOP & ZERO TOP ZERO
DSTOP Dual-slope PWM PER ZERO TOP –
Table 30-1. Counter Update and Overflow Event/Interrupt Conditions (Continued)
Description Description
Name Operation Top Update
Output
Waveform
On Match
Output
Waveform
On Update
OVFIF/Event
Up Down
Table 30-2. Waveform Generation Set/Clear Conditions
Waveform
Generation
operation
DIR POLx Waveform Generation Output Update
Set Clear
Single-Slope PWM
0
0 Timer/counter matches TOP Timer/counter matches CCx
1 Timer/counter matches CC Timer/counter matches TOP
1
0 Timer/counter matches CC Timer/counter matches ZERO
1 Timer/counter matches ZERO Timer/counter matches CC
Dual-Slope PWM x
0
Timer/counter matches CC when
counting up
Timer/counter matches CC when
counting down
1
Timer/counter matches CC when
counting down
Timer/counter matches CC when
counting up