Data Sheet

653
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181G–SAM-D21_Datasheet–09/2015
30.5 Product Dependencies
In order to use this peripheral, other parts of the system must be configured correctly, as described below.
30.5.1 I/O Lines
Using the TCC’s I/O lines requires the I/O pins to be configured. Refer to “PORT” on page 379 for details.
30.5.2 Power Management
The TCC will continue to operate in any sleep mode where the selected source clock is running. The TCC’s interrupts
can be used to wake up the device from sleep modes. Events connected to the event system can trigger other operations
in the system without exiting sleep modes. Refer to “PM – Power Manager” on page 117 for details on the different sleep
modes.
30.5.3 Clocks
The TCC bus clock (CLK_TCCx_APB, where x represents the specific TCC instance number) can be enabled and
disabled in the power manager, and the default state of CLK_TCCx_APB can be found in the Peripheral Clock Masking
section in “PM – Power Manager” on page 117
.
A generic clock (GCLK_TCCx) is required to clock the TCC. This clock must be configured and enabled in the generic
clock controller before using the TCC. Refer to “GCLK – Generic Clock Controller” on page 95 for details.
This generic clock is asynchronous to the bus clock (CLK_TCCx_APB). Due to this asynchronicity, writes to certain
registers will require synchronization between the clock domains. Refer to “Synchronization” on page 683 for further
details.
30.5.4 DMA
The DMA request lines are connected to the DMA Controller (DMAC). Using the TCC DMA requests, requires the DMA
Controller to be configured first. Refer to “DMAC – Direct Memory Access Controller” on page 272 for details.
30.5.5 Interrupts
The interrupt request line is connected to the Interrupt Controller. Using the TCC interrupts requires the interrupt
controller to be configured first. Refer to “Nested Vector Interrupt Controller” on page 34 for details.
30.5.6 Events
The events are connected to the Event System. Refer to “EVSYS – Event System” on page 406 for details on how to
configure the Event System.
30.5.7 Debug Operation
When the CPU is halted in debug mode the TCC will halt normal operation. The TCC can be forced to continue operation
during debugging. Refer to DBGCTRL for details.
30.5.8 Register Access Protection
All registers with write-access are optionally write-protected by the peripheral access controller (PAC), except the
following registers:
z Interrupt Flag register (INTFLAG)
z Status register (STATUS)
z Period and Period Buffer registers (PER, PERB)
z Compare/Capture and Compare/Capture Buffer registers (CCx, CCBx)
z Control Waveform and Control Waveform Buffer registers (WAVE, WAVEB)
z Pattern Generation Value and Pattern Generation Value Buffer registers (PATT, PATTB)