Data Sheet

643
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181G–SAM-D21_Datasheet–09/2015
29.8.11 Status
Name: STATUS
Offset: 0x0F
Reset: 0x08
Property: -
z Bit 7 – SYNCBUSY: Synchronization Busy
This bit is cleared when the synchronization of registers between the clock domains is complete.
This bit is set when the synchronization of registers between clock domains is started.
z Bits 6:5 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z Bit 4 – SLAVE: Slave
This bit is set when the even-numbered master TC is set to run in 32-bit mode. The odd-numbered TC will be the
slave.
z Bit 3 – STOP: Stop
This bit is set when the TC is disabled, on a Stop command or on an overflow or underflow condition when the
One-Shot bit in the Control B Set register (CTRLBSET.ONESHOT) is one.
0: Counter is running.
1: Counter is stopped.
z Bits 2:0 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
Bit76543210
SYNCBUSY SLAVE STOP
AccessRRRRRRRR
Reset00001000