Data Sheet

Atmel | SMART SAM D21 [DATASHEET]

Atmel-42181G–SAM-D21_Datasheet–09/2015

Table 29-8. TC Mode

z Bit 1 – ENABLE: Enable

0: The peripheral is disabled.

1: The peripheral is enabled.

Due to synchronization, there is delay from writing CTRLA.ENABLE until the peripheral is enabled/disabled. The

value written to CTRLA.ENABLE will read back immediately, and the Synchronization Busy bit in the Status regis-

ter (STATUS.SYNCBUSY) will be set. STATUS.SYNCBUSY will be cleared when the operation is complete.

z Bit 0 – SWRST: Software Reset

0: There is no reset operation ongoing.

1: The reset operation is ongoing.

Writing a zero to this bit has no effect.

Writing a one to this bit resets all registers in the TC, except DBGCTRL, to their initial state, and the TC will be

disabled.

Writing a one to CTRLA.SWRST will always take precedence; all other writes in the same write-operation will be

discarded.

Due to synchronization there is a delay from writing CTRLA.SWRST until the reset is complete. CTRLA.SWRST

and STATUS.SYNCBUSY will both be cleared when the reset is complete.

Value Name Description

0x0 COUNT16 Counter in 16-bit mode

0x1 COUNT8 Counter in 8-bit mode

0x2 COUNT32 Counter in 32-bit mode

0x3 - Reserved