Data Sheet

621
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181G–SAM-D21_Datasheet–09/2015
29.6.4 DMA, Interrupts and Events
Note: 1. Two DMA requests lines are available, one for each compare/capture channel.
29.6.4.1 DMA Operation
The TC can generate the following DMA requests:
z Overflow (OVF): the request is set when an update condition (overflow, underflow) is detected. The request is
cleared on next clock cycle.
z Channel Match or Capture (MCx): for a compare channel, the request is set on each compare match detection and
cleared on next clock cycle. For a capture channel, the request is set when valid data is present in CCx register,
and cleared when CCx register is read.
When using the TC with the DMA OVF request, the new value will be transfered to the register after the update condition.
This means that the value is updated after the DMA and synchronization delay, and if the COUNT value has reached the
new value before PER or CCx is updated, a match will not happen.
When using the TC with the DMA MCx request and updating CCx with a value that is lower than the current COUNT
when down-counting, or higher than the current COUNT when up-counting, this value could cause a new compare match
before the counter overflows. This will trigger the next DMA transfer, update CCx again, and the previous value is
disregarded from the output signal WO[x].
Table 29-1. Module Request for TC
Condition Interrupt request Event output Event input DMA request
DMA request is
cleared
Overflow /
Underflow
x x x
Cleared on next
clock cycle
Channel
Compare Match
or Capture
x x x
1
For compare
channel – Cleared
on next clock
cycle.
For capture
channel – cleared
when CCx
register is read
Capture Overflow
Error
x
Synchronization
Ready
x
Start Counter x
Retrigger
Counter
x
Increment /
Decrement
counter
x
Simple Capture x
Period Capture x
Pulse Width
Capture
x