Data Sheet

605
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181G–SAM-D21_Datasheet–09/2015
28.9.7 Serializer n Control
Name: SERCTRLn
Offset: 0x20+n*0x4 [n=0..1]
Reset: 0x00000000
Property: Enable-Protected, Write-Protected
z Bits 31:27 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z Bit 26 – RXLOOP: Loop-back Test Mode
This bit enables a loop-back test mode:
0: Each Receiver uses its SDn pin as input (default mode).
1: Receiver uses as input the transmitter output of the other Serializer in the pair: e.g. SD1 for SD0 or SD0 for SD1.
z Bit 25 – DMA: Single or Multiple DMA Channels
This bit selects whether even- and odd-numbered slots use separate DMA channels or the same DMA channel.
Refer to Table 28-12 for details.
Table 28-12. Single or Multiple DMA Channels
Bit 3130292827262524
RXLOOP DMA MONO
AccessRRRRRR/WR/WR/W
Reset00000000
Bit 2322212019181716
SLOTDIS7 SLOTDIS6 SLOTDIS5 SLOTDIS4 SLOTDIS3 SLOTDIS2 SLOTDIS1 SLOTDIS0
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
Bit 151413121110 9 8
BITREV EXTEND[1:0] WORDADJ
DATASIZE[2:0]
Access R/W R/W R/W R/W R R/W R/W R/W
Reset00000000
Bit 76543210
SLOTADJ
CLKSEL TXSAME TXDEFAULT[1:0] SERMODE[1:0]
Access R/W R R/W R/W R/W R/W R/W R/W
Reset00000000
DMA Name Description
0x0 SINGLE Single DMA channel
0x1 MULTIPLE One DMA channel per data channel