Data Sheet

602
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181G–SAM-D21_Datasheet–09/2015
28.9.5 Interrupt Flag Status and Clear
Name: INTFLAG
Offset: 0x14
Reset: 0x0000
Property: -
z Bits 15:14 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z Bits 13:12 – TXURx [x=1..0]: Transmit Underrun x
This flag is cleared by writing a one to it.
This flag is set when a Transmit Underrun condition occurs in Sequencer x, and will generate an interrupt request
if INTENCLR/SET.TXURx is set to one.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Transmit Underrun x interrupt flag.
z Bits 11:10 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z Bits 9:8 – TXRDYx [x=1..0]: Transmit Ready x
This flag is cleared by writing to DATAx register or writing a one to it.
This flag is set when Sequencer x is ready to accept a new data word to be transmitted, and will generate an inter-
rupt request if INTENCLR/SET.TXRDYx is set to one.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Transmit Ready x interrupt flag.
z Bits 7:6 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z Bits 5:4 – RXORx [x=1..0]: Receive Overrun x
This flag is cleared by writing a one to it.
This flag is set when a Receive Overrun condition occurs in Sequencer x, and will generate an interrupt request if
INTENCLR/SET.RXORx is set to one.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Receive Overrun x interrupt flag.
Bit 151413121110 9 8
TXUR1 TXUR0 TXRDY1 TXRDY0
Access R R R/W R/W R R R/W R/W
Reset00000000
Bit 76543210
RXOR1 RXOR0 RXRDY1 RXRDY0
Access R R R/W R/W R R R/W R/W
Reset00000000