Data Sheet

581
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181G–SAM-D21_Datasheet–09/2015
Slave Mode
In Slave mode, the Serial Clock and Frame Sync (Word Select in I
2
S mode and Frame Sync in TDM mode) are driven by
an external master. SCKn and FSn pins are inputs and no generic clock is required by the I
2
S.
Master Mode and Controller Mode
In Master Mode, Master Clock (MCKn), Serial Clock (SCKn), and Frame Sync Clock (FSn) are generated from the I
2
S
controller. The user can configure the Master Clock, Serial Clock, and Word Select Frame Sync signal (Word Select in
I
2
S mode and Frame Sync in TDM mode) using the Clock Control register (CLKCTRLn). MCKn, SCKn, and FSn pins are
outputs and a generic clock is used to derive the I
2
S clocks.
In some applications, audio codecs connected to the I
2
S pins may require a Master Clock signal with a frequency
multiple of the audio sample frequency (fs), such as 256fs.
In Controller mode, only the Clock generation unit needs to be configured in CTRLA and CLKCTRLn registers such as
clock division factors, Number of slots, Slot size, Frame Sync signal, clock enable.
MCKn Clock frequency
When the I
2
S is in Master mode, writing a one to CLKCTRLn.MCKEN will output GCLK_I2S_n as Master Clock to the
MCKn pin. The Master Clock to MCKn pin can be divided by configuring CLKCTRLn.MCKSEL and CLKCTRLn.
MCKOUTOUT. The Master Clock (MCKn) frequency is GCLK_I2S_n frequency divided by (MCLKOUTDIV+1).
SCKn Clock frequency
When the Serial Clock (SCKn) is generated from GCLK_I2S_n, by setting CLKCTRLn.MCKSEL and
CLKCTRLn.SCKSEL to zero, the Serial Clock (SCKn) frequency is GCLK_I2S_n frequency divided by (MCKDIV+1).
i.e. f(SCKn) = f(GCLK_I2S_n)/(MCKDIV +1)
Relation between MCKn, SCKn and sampling frequency(fs)
Based on sampling frequency (fs), SCKn frequency requirement can be calculated as per formula
given below.
SCKn frequency should be equal to .
As per configured number of slots and slot size, .
As per register configuration CLKCTRLn.NBSLOTS and CLKCTRLn.SLOTSIZE, Number of
slots and Slot size is configured.
The SLOTSIZE value will be 0x00 to 0x03 for configuring 8, 16, 24, or 32 bit slot and each frame is composed of
(NBSLOTS + 1) slots.
After considering all above mentioned formulas,
and
Now, MCKn frequency in terms of Sampling frequency (fs) is,
f MCKn()
fGCLK
I2S
–
n
–
()
MCKOUTDIV 1+()
----------------------------------------------------
=
Total number of bits per frame sampling frequency⋅
Total number of bits per frame Number of slots Slot size⋅=
Total Number of bits per frame 8 SLOTSIZE 1+()NBSLOTS 1+()⋅⋅=
f SCKn()8 SLOTSIZE 1+()NBSLOTS 1+()fs⋅⋅⋅=
f GCLK_I2S_n()f SCKn()MCKDIV 1+()8 SLOTSI ZE 1+()NBSLOTS 1+()⋅⋅ fs MCKDIV 1+()⋅⋅=⋅=
f GCLK_I2S_n()f MCKn()MCKOUTDIV 1+()⋅=