Data Sheet

577

Atmel | SMART SAM D21 [DATASHEET]

Atmel-42181G–SAM-D21_Datasheet–09/2015

28.5.7 Debug Operation

When the CPU is halted in debug mode the I

S continues the normal operation. If the I

S is configured such that it is

periodically serviced by the CPU through interrupts or other requests, it might result in improper operation or data loss

while debugging.

28.5.8 Register Access Protection

All registers with write-access are optionally write-protected by the Peripheral Access Controller (PAC), except the

following register:

z DATAm

z INTFLAG

z SYNCBUSY

Write-protection is denoted by the Write-protected property in the register description. Write-protection does not apply for

accesses through an external debugger. Refer to “PAC – Peripheral Access Controller” on page 41 for details.

28.5.9 Analog Connections

Not applicable.