Data Sheet

575
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181G–SAM-D21_Datasheet–09/2015
z Smart Data Holding register management to avoid data slots mix after overrun or underrun
28.3 Block Diagram
Figure 28-1. I
2
S Block Diagram
28.4 Signal Description
Serializers
SYSCTRL
Power
Manager
Peripheral
Bus
Bridge
DMA
Controller
Interrupt
Controller
Clock Units
Serializers
Peripheral Bus Interface
PORT
IRQ
Txm
Rxm
APB
APB clock
CLK_I2S_APB
2 Generic clocks
GCLK_I2S_0
GCLK_I2S_1
I
2
S
MCKn
SCKn
FSn
SDm
Table 28-1. Master Mode
Pin Name Pin Description Type
MCKn Master Clock for Clock Unit n Input/Output
SCKn Serial Clock for Clock Unit n Input/Output
FSn I
2
S Word Select or TDM Frame Sync for Clock Unit n Input/Output
SDm Serial Data Input or Output for Serializer m Input/Output
Table 28-2. Slave Mode
Pin Name Pin Description Type
MCKn Master Clock Input
SCKn Serial Clock for Clock Unit n Input
FSn I
2
S Word Select or TDM Frame Sync Input
SDm Serial Data Input or Output for Serializer m Input/Output