Data Sheet

570
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181G–SAM-D21_Datasheet–09/2015
1: High-speed transfer enabled.
z Bit 13 – LENEN: Transfer Length Enable
This bit enables automatic transfer length.
0: Automatic transfer length disabled.
1: Automatic transfer length enabled.
z Bits 12:11 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z Bits 10:0 – ADDR[10:0]: Address
When ADDR is written, the consecutive operation will depend on the bus state:
Unknown: INTFLAG.MB and STATUS.BUSERR are set, and the operation is terminated.
Busy: The I
2
C master will await further operation until the bus becomes idle.
Idle: The I
2
C master will issue a start condition followed by the address written in ADDR. If the address is acknowl-
edged, SCL is forced and held low, and STATUS.CLKHOLD and INTFLAG.MB are set.
Owner: A repeated start sequence will be performed. If the previous transaction was a read, the acknowledge
action is sent before the repeated start bus condition is issued on the bus. Writing ADDR to issue a repeated start
is performed while INTFLAG.MB or INTFLAG.SB is set.
Regardless of winning or loosing arbitration, the entire address will be sent. If arbitration is lost, only ones are
transmitted from the point of loosing arbitration and the rest of the address length.
STATUS.BUSERR, STATUS.ARBLOST, INTFLAG.MB and INTFLAG.SB will be cleared when ADDR is written.
The ADDR register can be read at any time without interfering with ongoing bus activity, as a read access does not
trigger the master logic to perform any bus protocol related operations.
The I
2
C master control logic uses bit 0 of ADDR as the bus protocol’s read/write flag (R/W); 0 for write and 1 for
read.
z Bits 31:24 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z Bits 23:16 – LEN[7:0]: Transaction Length
For DMA operation, this field represents the data length of the transaction from 0 to 255 bytes. The transaction
length enable (ADDR.LENEN) must be written to 1 for automatic transaction length to be used. After ADDR.LEN
bytes have been transmitted or received, a NACK (for master reads) and STOP are automatically generated.
z Bit 15 – TENBITEN: Ten Bit Addressing Enable
This bit enables 10-bit addressing. This bit can be written simultaneously with ADDR to indicate a 10-bit or 7-bit
address transmission.
0: 10-bit addressing disabled.
1: 10-bit addressing enabled.
z Bit 14 – HS: High Speed
This bit enables High-speed mode for the current transfer from repeated START to STOP. This bit can be written
simultaneously with ADDR for a high speed transfer.
0: .High-speed transfer disabled.
1: High-speed transfer enabled.
z Bit 13 – LENEN: Transfer Length Enable
This bit enables automatic transfer length.
0: Automatic transfer length disabled.
1: Automatic transfer length enabled.