Data Sheet

566
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181G–SAM-D21_Datasheet–09/2015
This bit is not write-synchronized.
z Bit 0 – BUSERR: Bus Error
The Bus Error bit (STATUS.BUSERR) indicates that an illegal bus condition has occurred on the bus, regardless
of bus ownership. An illegal bus condition is detected if a protocol violating start, repeated start or stop is detected
on the I
2
C bus lines. A start condition directly followed by a stop condition is one example of a protocol violation. If
a time-out occurs during a frame, this is also considered a protocol violation, and will set BUSERR.
If the I
2
C master is the bus owner at the time a bus error occurs, STATUS.ARBLOST and INTFLAG.MB will be set
in addition to BUSERR.
Writing the ADDR.ADDR register will automatically clear the BUSERR flag.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear it.
This bit is not write-synchronized.